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9: Debugging Your System
9.14.5
Scan chains 1 and 2
The scan chains enable serial access to the core logic, and to the EmbeddedICE-RT hardware
for programming purposes. Each scan chain cell is simple and comprises a serial register and
a multiplexor.
The scan cells perform three basic functions:
•
capture
•
shift
•
update.
For input cells, the capture stage involves copying the value of the system input to the core
into the serial register. During shift, this value is output serially. The value applied to the core
from an input cell is either the system input, or the contents of the parallel register (loads from
the shift register after UPDATE-DR state) under multiplexor control.
For output cells, capture involves placing the value of a core output into the serial register.
During shift, this value is serially output as before. The value applied to the system from an
output cell is either the core output, or the contents of the serial register.
All the control signals for the scan cells are generated internally by the TAP controller. The
action of the TAP controller is determined by current instruction and the state of the TAP state
machine.
Scan chain 1
Purpose
Length
Scan chain order
Scan chain 1, bit 33 serves three purposes:
•
Under normal INTEST test conditions, it enables a known value to be scanned into
the DBGBREAK input.
•
While debugging, the value placed in the 33rd bit determines whether the
ARM720T core synchronizes back to system speed before executing the instruction.
System speed access
See
•
After the ARM720T core has entered debug state, the value of the 33rd bit on the
first occasion that it is captured, and scanned out tells the debugger whether the
core entered debug state from a breakpoint (bit 33 LOW), or from a watchpoint (bit
33 HIGH).
Scan chain 2
Purpose
Length
Scan chain order
No action occurs during CAPTURE-DR.
9-24
Scan chain 1 is used for communication between the debugger, and
the ARM720T core. It is used to read and write data, and to scan
instructions into the pipeline. The SCAN_N TAP instruction can be
used to select scan chain 1.
33 bits, 32 bits a for the data value and 1 bit for the scan cell on the
DBGBREAK core input.
From DBGTDI to DBGTDO, the ARM720T processor data bits, bits
0 to 31, then the 33rd bit, the DBGBREAK scan cell.
on page 9-31 for more details.
Scan chain 2 provides access to the EmbeddedICE-RT registers. To
do this, scan chain 2 must be selected using the SCAN_N TAP
controller instruction, and then the TAP controller must be put in
INTEST mode.
38 bits.
From DBGTDI to DBGTDO, the read/write bit, the register
address bits, bits 4 to 0, then the data bits, bits 0 to 31.
EPSON
ARM720T CORE CPU MANUAL
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