Figure 2-3 Register Organization In Arm State - Epson ARM720T Core Cpu Manual

Interrupt modes
FIQ mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). In ARM state, many
FIQ handlers can use these banked registers to avoid having to save any registers onto a stack.
User, IRQ, Supervisor, Abort, and Undefined modes each have two banked registers, mapped
to r13 and r14, enabling each of these modes to have a private stack pointer and link registers.
System and User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
CPSR
= banked register
ARM720T CORE CPU MANUAL
ARM state general registers and program counter
FIQ Supervisor
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
r8_fiq r8
r9_fiq r9
r10_fiq r10
r11_fiq r11
r12_fiq r12
r13_fiq r13_svc
r14_fiq r14_svc
r15 (PC) r15 (PC)
ARM state program status registers
CPSR CPSR
SPSR_fiq SPSR_svc

Figure 2-3 Register organization in ARM state

EPSON
2: Programmer's Model
Abort IRQ
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13_abt r13_irq
r14_abt r14_irq
r15 (PC) r15 (PC)
CPSR CPSR
SPSR_abt SPSR_irq
Undefined
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_und
r14_und
r15 (PC)
CPSR
SPSR_und
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