Table 9-5 Scan Chain Number Allocation - Epson ARM720T Core Cpu Manual

9.14.3 Instruction register
Purpose
Length
Operating mode
9.14.4 Scan path select register
Purpose
Length
Operating mode
Table 9-5 shows the scan chain number allocation.
ARM720T CORE CPU MANUAL
Changes the current TAP instruction.
4 bits.
In the SHIFT-IR state, the instruction register is selected as the
serial path between DBGTDI, and DBGTDO.
During the CAPTURE-IR state, the binary value 0001 is loaded
into this register. This value is shifted out during SHIFT-IR (least
significant bit first), while a new instruction is shifted in (least
significant bit first).
During the UPDATE-IR state, the value in the instruction register
becomes the current instruction.
On reset, IDCODE becomes the current instruction.
There is no parity bit.
Changes the current active scan chain.
4 bits.
SCAN_N as the current instruction in the SHIFT-DR state selects
the scan path select register as the serial path between DBGTDI,
and DBGTDO.
During the CAPTURE-DR state, the value b1000 binary is loaded
into this register. This value is loaded out during SHIFT-DR (least
significant bit first), while a new value is loaded in (least
significant bit first). During the UPDATE-DR state, the value in
the register selects a scan chain to become the currently active scan
chain. All additional instructions, such as INTEST, then apply to
that scan chain.
The currently-selected scan chain changes only when a SCAN_N
instruction is executed, or when a reset occurs. On reset, scan chain
0 is selected as the active scan chain.

Table 9-5 Scan chain number allocation

Scan chain number Function
0 (User-implemented)
1 Debug
2 EmbeddedICE-RT
programming
3 Reserved
4 Reserved
8 Reserved
a. When selected, reserved scan
chains scan out zeros.
EPSON
9: Debugging Your System
a
a
a
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