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7.8
External aborts
In addition to the MMU-generated aborts, the ARM720T processor can be externally aborted
by the AMBA bus. This can be used to flag an error on an external memory access. However,
not all accesses can be aborted in this way and the
aborts that cannot be handled.
The following accesses can be aborted:
•
noncached reads
•
unbuffered writes
•
read-lock-write sequence, to noncachable memory.
In the case of a read-lock-write (SWP) sequence, if the read aborts, the write is never
attempted.
7.9
Interaction of the MMU and cache
The MMU is enabled and disabled using bit 0 of the CP15 Control Register c1 as described in:
Enabling the MMU
•
Disabling the MMU
•
7.9.1
Enabling the MMU
To enable the MMU:
1
Program the TTB and Domain Access Control Registers.
2
Program level 1 and level 2 page tables as required.
3
Enable the MMU by setting bit 0 in the control register.
You must take care if the translated address differs from the untranslated address because
several instructions following the enabling of the MMU might have been prefetched with the
MMU off (using physical = VA - flat translation).
In this case, enabling the MMU can be considered as a branch with delayed execution. A
similar situation occurs when the MMU is disabled. Consider the following code sequence:
MRC p15, 0, r1, c1, c0, 0
ORR R1, R1, #0x01
MCR p15,0, r1, c1, c0, 0
Fetch Flat
Fetch Flat
Fetch Translated
7.9.2
Disabling the MMU
To disable the MMU, clear bit 0 in the control register. The data cache must be disabled prior
to, or at the same time as, the MMU is disabled by clearing bit 2 of the control register. See
Enabling the MMU
regarding prefetch effects.
If the MMU is enabled, then disabled and subsequently re-enabled, the contents of
Note:
the TLB are preserved. If these are now invalid, you must invalidate the TLB before
re-enabling the MMU. See
ARM720T CORE CPU MANUAL
Bus Interface Unit
.
; Read control register
; Enable MMUS
TLB Operations Register
EPSON
7: Memory Management Unit
(BIU) ignores external
on page 3-7.
7-21
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