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9: Debugging Your System
9.14
Test data registers
The six test data registers that can connect between DBGTDI and DBGTDO are described in
the following sections:
Bypass register
•
ARM720T processor device identification (ID) code register
•
Instruction register
•
Scan path select register
•
Scan chain 1
•
Scan chain 2
•
In the following descriptions, data is shifted during every HCLK cycle when DBGTCKEN
enable is HIGH.
9.14.1
Bypass register
Purpose
Length
Operating mode
9.14.2
ARM720T processor device identification (ID) code register
Purpose
Length
The default device identification code is 0x7f1f0f0f.
Operating mode
9-22
on page 9-23
on page 9-23
on page 9-17
on page 9-17.
Bypasses the device during scan testing by providing a path
between DBGTDI and DBGTDO.
1 bit.
When the BYPASS instruction is the current instruction in the
instruction register, serial data is transferred from DBGTDI to
DBGTDO in the SHIFT-DR state with a delay of one HCLK cycle
enabled by DBGTCKEN.
There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in
the CAPTURE-DR state.
Reads the 32-bit device identification code. No programmable
supplementary identification code is provided.
32 bits. The format of the ID code register is as shown in
Figure 9-9.
31
28
27
Version
Figure 9-9 ID code register format
When the IDCODE instruction is current, the ID register is
selected as the serial path between DBGTDI and DBGTDO.
There is no parallel output from the ID register.
The 32-bit device identification code is loaded into the ID register
from its parallel inputs during the CAPTURE-DR state.
EPSON
Part number
ARM720T CORE CPU MANUAL
12
11
Manufacturer identity
1
0
1
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