Figure 3-9 Fault Address Register Format; Table 3-2 Cache Operation; Table 3-3 Tlb Operations - Epson ARM720T Core Cpu Manual

3.3.6 Fault Address Register
Reading CP15 Register 6 returns the value of the
holds the virtual address of the access that was attempted when a fault occurred. The FAR is
only updated on data faults. There is no update on prefetch faults.
Writing to CP15 Register 6 sets the FAR to the value of the data written. This is useful when
a debugger has to restore the value of the FAR.
The CRm and opcode_2 fields Should Be Zero when reading or writing CP15 Register 6. Fault
Address Register format is shown in Figure 3-9.
31
Register 6 contains a modified virtual address if the FCSE PID register is nonzero.
Note:
3.3.7 Cache Operations Register
Writing to CP15 Register 7 manages the unified instruction and data cache of the ARM720T.
Only one cache operation is defined using the following opcode_2 and CRm fields in the MCR
instruction that writes the CP15 Register 7.
Caution: The Invalidate ID cache function invalidates all cache data. Use this with caution.
Register 7 is shown in Table 3-2.
Function
Invalidate ID
cache
Reading from CP15 Register 7 is undefined.
3.3.8 TLB Operations Register
Writing to CP15 Register 8 controls the
processor implements a unified instruction and data TLB.
Two TLB operations are defined. The function to be performed is selected by the opcode_2 and
CRm fields in the MCR instruction used to write CP15 Register 8.
The TLB operations and the instructions that you can use are shown in Table 3-3.
Function opcode_2 value
Invalidate TLB b000
Invalidate TLB b001
single entry
ARM720T CORE CPU MANUAL
Fault address

Figure 3-9 Fault Address Register format

Table 3-2 Cache operation

opcode_2 value CRm value
b000 b0111
Translation Lookaside Buffer

Table 3-3 TLB operations

CRm value
b1000
b1000
Fault Address Register
Data Instruction
SBZ MCR p15, 0, <Rd>, c7, c7, 0
Data
SBZ
Modified Virtual
Address
EPSON
3: Configuration
(FAR). The FAR
00
(TLB). The ARM720T
Instruction
MCR p15, 0, <Rd>, c8, c5, 0
MCR p15, 0, <Rd>, c8, c6, 0
MCR p15, 0, <Rd>, c8, c7, 0
MCR p15, 0, <Rd>, c8, c5, 1
MCR p15, 0, <Rd>, c8, c6, 1
MCR p15, 0, <Rd>, c8, c7, 1
3-7