Figure 8-4 Coprocessor Load Sequence - Epson ARM720T Core Cpu Manual

8: Coprocessor Interface
8.4.7 Coprocessor load and store operations
The coprocessor load and store instructions, LDC and STC, are used to transfer data between
a coprocessor and memory. They can be used to transfer either a single word of data or a
number of the coprocessor registers. There is no limit to the number of words of data that can
be transferred by a single LDC or STC instruction, but by convention a coprocessor must not
transfer more than 16 words of data in a single instruction. An example sequence is shown in
Figure 8-4.
Note:
The external coprocessor must not abort on LDC and STC instructions unless
•
they can be decoded as a CP15 operations otherwise dead lock occurs on busy
waiting.
If you transfer more than 16 words of data in a single instruction, the
•
worst-case interrupt latency of the ARM720T processor increases.
HCLK
Fetch
ADD
stage
Decode
stage
Execute
stage
CPnCPI
(from core)
EXTCPA
(from coprocessor)
EXTCPB
(from coprocessor)
I Fetch
HRDATA[31:0] (ADD)
8-8
SUB LDC TST
n=4
ADD SUB LDC
ADD SUB
I Fetch I Fetch I Fetch
(SUB) (CPDO) (TST) (SWINE)

Figure 8-4 Coprocessor load sequence

EPSON
SWINE
TST
LDC
I Fetch CP data CP data CP data
SWINE
TST SWINE
CP data I Fetch
ARM720T CORE CPU MANUAL