Table 2-2 Psr Mode Bit Values - Epson ARM720T Core Cpu Manual

2.7.3 Reserved bits
The remaining bits in the PSRs are reserved. When changing flag or control bits of a PSR, you
must ensure that these unused bits are not altered. Also, your program must not rely on them
containing specific values, because in future processors they might read as one or zero.
M[4:0] Mode
b10000 User
b10001 FIQ
b10010 IRQ
b10011 Supervisor
b10111 Abort
b11011 Undefined
b11111 System
ARM720T CORE CPU MANUAL

Table 2-2 PSR mode bit values

Visible Thumb state registers
r7 to r0,
LR, SP
PC, CPSR
r7 to r0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
r7 to r0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
r7 to r0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
r7 to r0,
LR_abt, SP_abt,
PC, CPSR, SPSR_abt
r7 to r0
LR_und, SP_und,
PC, CPSR, SPSR_und
r7 to r0,
LR, SP
PC, CPSR
EPSON
2: Programmer's Model
Visible ARM state registers
r14 to r0,
PC, CPSR
r7 to r0,
r14_fiq..r8_fiq,
PC, CPSR, SPSR_fiq
r12 to r0,
r14_irq, r13_irq,
PC, CPSR, SPSR_irq
r12 to r0,
r14_svc, r13_svc,
PC, CPSR, SPSR_svc
r12 to r0,
r14_abt..r13_abt,
PC, CPSR, SPSR_abt
r12 to r0,
r14_und, r13_und,
PC, CPSR, SPSR_und
r14 to r0,
PC, CPSR
2-9