Figure 6-1 Simple Ahb Transfer - Epson ARM720T Core Cpu Manual

6: The Bus Interface
Figure 6-1 shows a transfer with no wait states (this is the simplest type of transfer).
A granted bus master starts an AHB transfer by driving the address and control signals.
These signals provide the following information about the transfer:
• address
• direction
• width of the transfer
• whether the transfer forms part of a burst
• the type of burst.
A burst is a series of transfers. The ARM720T processor performs the following types of burst:
• Incrementing burst of unspecified length.
• 8-beat incrementing burst only used during linefill.
Incrementing bursts do not wrap at address boundaries. The address of each
transfer in the burst is an increment of the address of the previous transfer in the
burst.
For more information, see
For a complete description of the AHB transfer mechanism, see the
2.0)
.
6-2
Address
phase
HCLK
HADDR[31:0]
Control
HWDATA[31:0]
HREADY
HRDATA[31:0]

Figure 6-1 Simple AHB transfer

Address and control signals
EPSON
Data
phase
A
Control
Data
(A)
Data (A)
on page 6-7.
ARM720T CORE CPU MANUAL
AMBA Specification (Rev