Figure 3-7 Domain Access Control Register Format; Figure 3-8 Fault Status Register Format - Epson ARM720T Core Cpu Manual

3: Configuration
3.3.4 Domain Access Control Register
Reading from CP15 Register 3 returns the value of the Domain Access Control Register.
Writing to CP15 Register 3 writes the value of the Domain Access Control Register.
The Domain Access Control Register consists of 16 2-bit fields, each of which defines the access
permissions for one of the 16 domains (D15-D0).
The CRm and opcode_2 fields Should Be Zero when reading or writing to CP15 Register 3.
Domain Access Control Register format is shown in Figure 3-7.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
D15 D14
3.3.5 Fault Status Register
Reading CP15 Register 5 returns the value of the
contains the source of the last fault.
Only the bottom 9 bits are returned. The upper 23 bits are Unpredictable.
Note:
The FSR indicates the domain and type of access being attempted when an abort occurred:
Bit 8
Bits [7:4]
Bits [3:1]
The encoding of these bits is shown in
The FAR is only updated on data faults. There is no update on prefetch faults.
Writing to CP15 Register 5 sets the FSR to the value of the data written. This is useful when
a debugger has to restore the value of the FSR. The upper 24 bits written Should Be Zero.
The CRm and opcode_2 fields Should Be Zero when reading or writing CP15 Register 5. Fault
Status Register format is shown in Figure 3-8.
31 30
3-6
D13 D12 D11 D10 D9

Figure 3-7 Domain Access Control Register format

This is always read as zero. Bit 8 is ignored on writes.
These specify which of the 16 domains (D15-D0) was being accessed
when a fault occurred.
These indicate the type of access being attempted.
Fault address and fault status registers
UNP/SBZ

Figure 3-8 Fault Status Register format

D8 D7 D6 D5 D4
Fault Status Register
09 08 07 06
0
EPSON
D3 D2 D1 D0
(FSR). The FSR
on page 7-16.
04 03 00
Domain Status
ARM720T CORE CPU MANUAL