The Program Counter During Debug - Epson ARM720T Core Cpu Manual

9: Debugging Your System
Figure 9-3 on page 9-5 shows that the final memory access occurs in the cycle after DBGACK
goes HIGH. This is the point at which the cycle counter must be disabled. Figure 9-11 on
page 9-29 shows that the first memory access that the cycle counter has not previously seen
occurs in the cycle after DBGACK goes LOW. This is the point at which to re-enable the
counter.
When a system speed access from debug state occurs, the ARM720T processor
Note:
temporarily drops out of debug state, so DBGACK can go LOW. If there are
peripherals that are sensitive to the number of memory accesses, they must be led
to believe that the ARM720T processor is still in debug state. You can do this by
programming the EmbeddedICE-RT control register to force the value on DBGACK
to be HIGH. See
9.18

The program counter during debug

The debugger must keep track of what happens to the PC, so that the ARM720T core can be
forced to branch back to the place at which program flow was interrupted by debug. Program
flow can be interrupted by any of the following:
Breakpoints
•
Watchpoints
•
Watchpoint with another exception
•
Debug request
•
System speed access
•
9.18.1 Breakpoints
Entry into debug state from a breakpoint advances the PC by four addresses or 16 bytes. Each
instruction executed in debug state advances the PC by one address or 4 bytes.
The usual way to exit from debug state after a breakpoint is to remove the breakpoint and
branch back to the previously-breakpointed address.
For example, if the ARM720T processor entered debug state from a breakpoint set on a given
address, and two debug speed instructions were executed, a branch of –7 addresses must occur
(4 for debug entry, plus 2 for the instructions, plus 1 for the final branch).
The following sequence shows the data scanned into scan chain 1, most significant bit first.
The value of the first digit goes to the DBGBREAK bit, and then the instruction data into the
remainder of scan chain 1:
0 E0802000; ADD r2, r0, r0
1 E1826001; ORR r6, r2, r1
0 EAFFFFF9; B -7 (2's complement)
After the ARM720T processor enters debug state, it must execute a minimum of two
instructions before the branch, although these can both be NOPs (MOV R0, R0). For small
branches, you can replace the final branch with a subtract, with the PC as the destination
(SUB PC, PC, #28 in the above example).
9.18.2 Watchpoints
The return to program execution after entry to debug state from a watchpoint is made in the
same way as the procedure described in
Debug entry adds four addresses to the PC, and every instruction adds one address. The
difference from breakpoint is that the instruction that caused the watchpoint has executed,
and the program must return to the next instruction.
9-30
Debug status register
on page 9-31
on page 9-31
Breakpoints
EPSON
on page 9-41 for more details.
on page 9-31
.
ARM720T CORE CPU MANUAL