Table 2-3 Exception Entry And Exit - Epson ARM720T Core Cpu Manual

2.8.2 Action on leaving an exception
On completion, the exception handler:
1 Moves the LR, minus an offset where appropriate, to the PC. The offset varies
depending on the type of exception.
2 Copies the SPSR back to the CPSR.
3 Clears the interrupt disable flags, if they were set on entry.
An explicit switch back to Thumb state is never necessary, because restoring the
Note:
CPSR from the SPSR automatically sets the T bit to the value it held immediately
prior to the exception.
2.8.3 Exception entry and exit summary
Table 2-3 summarizes the PC value preserved in the relevant r14 register on exception entry,
and the recommended instruction for exiting the exception handler.
Exception
a
BL
a
SWI
UDEF
b
FIQ
b
IRQ
PABT
DABT
RESET
a.
b.
c.
d.
ARM720T CORE CPU MANUAL

Table 2-3 Exception entry and exit

Return instruction
MOV PC, r14
MOVS PC, r14_svc
a
MOVS PC, r14_und
SUBS PC, r14_fiq, #4
SUBS PC, r14_irq, #4
a
SUBS PC, r14_abt, #4
c
SUBS PC, r14_abt, #8
d
NA
PC is the address of the BL,
SWI, Undefined Instruction, or Fetch, that had the Prefetch Abort.
PC is the address of the instruction that was not executed
because the FIQ or IRQ took priority.
PC is the address of the Load or Store instruction that
generated the Data Abort.
The value saved in r14_svc upon reset is Unpredictable.
Previous state
ARM r14_x
PC + 4
PC + 4
PC + 4
PC + 4
PC + 4
PC + 4
PC + 8
-
EPSON
2: Programmer's Model
Thumb r14_x
PC + 2
PC + 2
PC + 2
PC + 4
PC + 4
PC + 4
PC + 8
-
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