Registers; Figure 3-2 Id Register Read Format; Figure 3-3 Id Register Write Format; Table 3-1 Cache And Mmu Control Register - Epson ARM720T Core Cpu Manual

3.3

Registers

The ARM720T processor contains registers that control the cache and MMU operation. You
can access these registers using MCR and MRC instructions to CP15 with the processor in a
privileged mode.
Table 3-1 shows a summary of valid CP15 registers. You must not attempt to read from, or to
write to, an invalid register because it results in Unpredictable behavior.
Register Register reads
0 ID Register
1 Control Register
2 Translation Table Base Register
3 Domain Access Control Register
4 Reserved
5 Fault Status Register
6 Fault Address Register
7 Reserved
8 Reserved
9 – 12 Reserved
13 Process Identifier Register
14 Reserved
15 Test Registers
3.3.1 ID Register
Reading from CP15 Register 0 returns the value:
0x41807204
The final nibble represents the core revision.
Note:
The CRm and opcode_2 fields Should Be Zero when reading CP15 register 0. ID Register read
format is shown in Figure 3-2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 1 0 0
Writing to CP15 register 0 is Unpredictable. ID Register write format is shown in Figure 3-3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARM720T CORE CPU MANUAL

Table 3-1 Cache and MMU Control Register

0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1

Figure 3-2 ID Register read format

Figure 3-3 ID Register write format

EPSON
Register writes
Reserved
Control Register
Translation Table Base Register
Domain Access Control Register
Reserved
Fault Status Register
Fault Address Register
Cache Operations Register
TLB Operations Register
Reserved
Process Identifier Register
Reserved
Test Registers
0 0 1 0 0 0 0 0 0 1 0 0
UNP
3: Configuration
3-3