Fault Checking Sequence; Figure 7-14 Sequence For Checking Faults - Epson ARM720T Core Cpu Manual

7.7

Fault checking sequence

The sequence the MMU uses to check for access faults is different for sections and pages. The
sequence for both types of access is shown in Figure 7-14.
Section
translation
fault
Section
domain
fault
Section
permission
fault
The conditions that generate each of the faults are described in:
Alignment fault
•
Translation fault
•
Domain fault
•
Permission fault
•
7.7.1 Alignment fault
If alignment fault is enabled (A bit in CP15 register c1 set), the MMU generates an alignment
fault on any data word access, if the address is not word-aligned, or on any halfword access, if
the address is not halfword-aligned, irrespective of whether the MMU is enabled or not. An
alignment fault is not generated on any instruction fetch, nor on any byte access.
If the access generates an alignment fault, the access sequence aborts without
Note:
reference to more permission checks.
ARM720T CORE CPU MANUAL
Modified virtual address
Check address alignment
Invalid Get level one descriptor
Section
No access (00)
Check domain status
Reserved (10)
Section
Client (01)
Check
Violation access
permissions
Physical address

Figure 7-14 Sequence for checking faults

on page 7-19
on page 7-20
on page 7-20
on page 7-20
Misaligned
Page
Get page
table entry
No access (00)
Reserved (10)
Page
Client (01)
Manager
(11)
Check
access Violation
permissions
EPSON
7: Memory Management Unit
Alignment
fault
Page
Invalid
translation
fault
Page
domain
fault
Page
permission
fault
7-19