Page 1 ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL...
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is appli- cable to products requiring high level reliability, such as medical products.
Page 3 Preface Introduction Programmer’s Model Configuration Instruction and Data Cache Write Buffer The Bus Interface Memory Management Unit Coprocessor Interface Debugging Your System 10 ETM Interface 11 Test Support Signal Descriptions Glossary Index...
Page 5: Table Of Contents
About the bus interface................6-1 Bus interface signals ................. 6-3 Transfer types.................... 6-5 Address and control signals ..............6-7 Slave transfer response signals ..............6-9 Data buses ....................6-10 Arbitration ....................6-12 Bus clocking .................... 6-13 ARM720T CORE CPU MANUAL EPSON...
Page 6 Programming breakpoints................ 9-36 9.22 Programming watchpoints ............... 9-38 9.23 Abort status register................. 9-38 9.24 Debug control register ................9-39 9.25 Debug status register................9-41 9.26 Coupling breakpoints and watchpoints ............ 9-43 9.27 EmbeddedICE-RT timing................. 9-44 EPSON ARM720T CORE CPU MANUAL...
Page 7 MMU test registers and operations............11-8 Signal Descriptions AMBA interface signals ................A-1 Coprocessor interface signals ..............A-2 JTAG and test signals ................A-3 Debugger signals..................A-4 Embedded trace macrocell interface signals ..........A-5 ATPG test signals..................A-7 Miscellaneous signals................A-7 Glossary Index ARM720T CORE CPU MANUAL EPSON...
Page 8 Figure 8-4 Coprocessor load sequence ............... 8-8 Figure 8-5 Example coprocessor connections ............. 8-9 Figure 9-1 Typical debug system ................. 9-2 Figure 9-2 ARM720T processor block diagram ............9-3 Figure 9-3 Debug state entry..................9-5 EPSON ARM720T CORE CPU MANUAL...
Page 9 Rd format, RAM1 write................11-10 Figure 11-14 Data format, RAM1 read ................. 11-11 Figure 11-15 Rd format, RAM2 write and data format, RAM2 read ......11-11 Figure 11-16 Rd format, write TLB lockdown ............... 11-12 ARM720T CORE CPU MANUAL EPSON...
Page 10 Domain Access Control Register bit assignments ........9-15 Table 9-3 Instruction encodings for scan chain 15............ 9-18 Table 9-4 Public instructions ..................9-20 Table 9-5 Scan chain number allocation ..............9-23 Table 9-6 Scan chain 1 cells ..................9-25 EPSON ARM720T CORE CPU MANUAL...
Page 11 Coprocessor interface signal descriptions ..........A-2 Table A-3 JTAG and test signal descriptions...............A-3 Table A-4 Debugger signal descriptions..............A-4 Table A-5 ETM interface signal descriptions ...............A-5 Table A-6 ATPG test signal descriptions ..............A-7 Table A-7 Miscellaneous signal descriptions...............A-7 ARM720T CORE CPU MANUAL EPSON...
Page 12 CONTENTS THIS PAGE IS BLANK. viii EPSON ARM DDI 0229B...
Page 13 Preface...
Page 15: About This Document
Read this chapter for a description of the ARM720T processor bus interface. Memory Management Unit Chapter 7 Read this chapter for a description of the functions and how to use Memory Management Unit of the (MMU). ARM720T CORE CPU MANUAL EPSON...
Page 16 Product revision status The r identifier indicates the revision status of the product described in this document, where: Identifies the major revision of the product. Identifies the minor revision or modification status of the product. EPSON ARM720T CORE CPU MANUAL...
Page 17 Figure 9-8 on page 9-19 is printed with permission IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. ARM720T CORE CPU MANUAL EPSON xiii...
Page 18 Preface THIS PAGE IS BLANK. EPSON ARM720T CORE CPU MANUAL...
Page 19: Introduction
Introduction...
Page 21: About The Arm720T Processor
This makes it ideal for portable applications where low power consumption is essential. Reduced Instruction Set Computer The ARM720T processor architecture is based on (RISC) principles. The instruction set and related decode mechanism are greatly simplified compared Complex Instruction Set Computers with microprogrammed (CISCs). ARM720T CORE CPU MANUAL EPSON...
Page 22: Figure 1-1 720T Block Diagram
Internal data bus Data and Control and System control address clocking logic coprocessor buf f ers A MBA interf ace A RM720T A MBA A HB bus interf ace Figure 1-1 720T Block diagram EPSON ARM720T CORE CPU MANUAL...
Page 23: Figure 1-2 Arm720T Processor Functional Signals
The EmbeddedICE-RT logic contains a (DCC). The DCC is used to pass information between the target and the host debugger. The EmbeddedICE-RT Joint Test Action Group logic is controlled through the (JTAG) test access port. ARM720T CORE CPU MANUAL EPSON...
Page 24 Prefetch or Data Abort exception because of a real abort, or because of a Abort status register breakpoint or watchpoint. For more details, see on page 9-38. Debugging Your System For more details, see Chapter 9 EPSON ARM720T CORE CPU MANUAL...
Page 25: Coprocessors
The ARM instruction set is a good target for compilers of many different high-level languages. Where required for critical code segments, assembly code programming is also straightforward. ARM720T CORE CPU MANUAL EPSON...
Page 26: Table 1-1 Key To Tables
Refer to Table 1-8 on page 1-12. #<32bit_Imm> A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. <reglist> A comma-separated list of registers, enclosed in braces ( { and } ). EPSON ARM720T CORE CPU MANUAL...
Page 27: Figure 1-3 Arm Instruction Set Formats
Some instruction codes are not defined but do not cause the Undefined instruction Note: trap to be taken, for example, a multiply instruction with bit 6 set. You must not use these instructions, because their action might change in future ARM implementations. ARM720T CORE CPU MANUAL EPSON...
Page 28: Table 1-2 Arm Instruction Summary
TEQ{cond} <Rn>, <Oprnd2> AND{cond}{S} <Rd>, <Rn>, <Oprnd2> EOR{cond}{S} <Rd>, <Rn>, <Oprnd2> ORR{cond}{S} <Rd>, <Rn>, <Oprnd2> Bit clear BIC{cond}{S} <Rd>, <Rn>, <Oprnd2> Branch Branch B{cond} <label> Branch with link BL{cond} <label> Branch, and exchange instruction BX{cond} <Rn> EPSON ARM720T CORE CPU MANUAL...
Page 29 Increment after STM{cond}IA <Rd>{!}, <reglist>{^} Decrement before STM{cond}DB <Rd>{!}, <reglist>{^} Decrement after STM{cond}DA <Rd>{!}, <reglist>{^} Stack operations STM{cond}<a_mode4S> <Rd>{!}, <reglist> User registers STM{cond}<a_mode4S> <Rd>{!}, <reglist>^ Swap Word SWP{cond} <Rd>, <Rm>, [<Rn>] Byte SWP{cond}B <Rd>, <Rm>, [<Rn>] ARM720T CORE CPU MANUAL EPSON...
Page 30: Table 1-3 Addressing Mode 2
[<Rn>, +/-<Rm>, RRX]! Post-indexed immediate offset [<Rn>], #+/-<12bit_Offset> Post-indexed register offset [<Rn>], +/-<Rm> Post-indexed scaled register offset [<Rn>], +/-<Rm>, LSL #<5bit_shift_imm> [<Rn>], +/-<Rm>, LSR #<5bit_shift_imm> [<Rn>], +/-<Rm>, ASR #<5bit_shift_imm> [<Rn>], +/-<Rm>, ROR #<5bit_shift_imm> [<Rn>, +/-<Rm>, RRX] 1-10 EPSON ARM720T CORE CPU MANUAL...
Page 31: Table 1-4 Addressing Mode 2 (Privileged)
Addressing mode 4 (load), <a_mode4L>, is shown in Table 1-6. Table 1-6 Addressing mode 4 (load) Addressing mode Stack type Increment after Full descending Increment before Empty descending Decrement after Full ascending Decrement before Empty ascending ARM720T CORE CPU MANUAL EPSON 1-11...
Page 32: Table 1-7 Addressing Mode 4 (Store)
Fields, {field}, are shown in Table 1-10. Table 1-10 Fields Suffix Sets Control field mask bit (bit 3) Flags field mask bit (bit 0) Status field mask bit (bit 1) Extension field mask bit (bit 2) 1-12 EPSON ARM720T CORE CPU MANUAL...
Page 33: Table 1-11 Condition Fields
Greater than Z clear, N=V (N and V set or N and V clear) Less than, or equal Z set or N<>V (N set and V clear) or (N clear and V set) Always Always ARM720T CORE CPU MANUAL EPSON 1-13...
Page 34: Figure 1-4 Thumb Instruction Set Formats
1 1 0 Offset11 Long branch with link 1 1 1 Offset 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Figure 1-4 Thumb instruction set formats 1-14 EPSON ARM720T CORE CPU MANUAL...
Page 35: Table 1-12 Thumb Instruction Summary
Compare Negative CMN <Rd>, <Rs> Compare Immediate CMP <Rd>, #<8bit_Imm> Logical AND <Rd>, <Rs> EOR <Rd>, <Rs> ORR <Rd>, <Rs> Bit clear BIC <Rd>, <Rs> Move NOT MVN <Rd>, <Rs> Test bits TST <Rd>, <Rs> ARM720T CORE CPU MANUAL EPSON 1-15...
Page 36 Lo reg BX <Rs> to address held in Hi reg BX <Hs> Load With immediate offset word LDR <Rd>, [<Rb>, #<7bit_offset>] halfword LDRH <Rd>, [<Rb>, #<6bit_offset>] byte LDRB <Rd>, [<Rb>, #<5bit_offset>] 1-16 EPSON ARM720T CORE CPU MANUAL...
Page 37 Pop registers from stack POP <reglist> Pop registers, and PC POP <reglist, PC> from stack Software SWI <8bit_Imm> Interrupt All thumb fetches are done as 32-bit bus transactions using the 32-bit thumb Note: prefetch buffer. ARM720T CORE CPU MANUAL EPSON 1-17...
Page 38: Silicon Revisions
1: Introduction Silicon revisions Product revision status This manual is for revision r4p2 of the ARM720T macrocell. See page xii for details of revision numbering. There are no functional differences from previous revisions. 1-18 EPSON ARM720T CORE CPU MANUAL...
Page 39: Programmer's Model
Programmer’s Model...
Page 41: Processor Operating States
On the processor taking an exception, for example, IRQ, FIQ, RESET, UNDEF, ABORT, and SWI. In this case, the PC is placed in the link register of the exception mode, and execution starts at the vector address of the exception. ARM720T CORE CPU MANUAL EPSON...
Page 42: Memory Formats
16 15 address Higher address Lower address Figure 2-1 Big-endian addresses of bytes with words Note: • Most significant byte is at lowest address • Word is addressed by byte address of most significant byte. EPSON ARM720T CORE CPU MANUAL...
Page 43: Instruction Length
(8-bit) • halfword (16-bit) • word (32-bit). You must align these as follows: • word quantities to 4-byte boundaries • halfwords quantities to 2-byte boundaries • byte quantities can be placed on any byte boundary. ARM720T CORE CPU MANUAL EPSON...
Page 44: Operating Modes
0 is zero and bits [31:1] contain the PC. Current Program Status Register In addition to these, the (CPSR) is used to store status information. It contains condition code flags and the current mode bits. EPSON ARM720T CORE CPU MANUAL...
Page 45: Figure 2-3 Register Organization In Arm State
(PC) r15 (PC) r15 (PC) r15 (PC) r15 (PC) ARM state program status registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und = banked register Figure 2-3 Register organization in ARM state ARM720T CORE CPU MANUAL EPSON...
Page 46: Figure 2-4 Register Organization In Thumb State
SP_svc SP_abt SP_irq SP_und LR_fiq LR_svc LR_abt LR_irq LR_und Thumb state program status registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und = banked register Figure 2-4 Register organization in Thumb state EPSON ARM720T CORE CPU MANUAL...
Page 47: Figure 2-5 Mapping Of Thumb State Registers Onto Arm State Registers
MOV instruction. High register values can also be compared against or added to low register values ARM Architecture Reference Manual with the CMP and ADD instructions. See the for details on high register operations. ARM720T CORE CPU MANUAL EPSON...
Page 48: Program Status Registers
Only those explicitly described can be used. If you program any illegal value into the mode bits, M[4:0], then the processor Note: enters an unrecoverable state. If this occurs, apply reset. EPSON ARM720T CORE CPU MANUAL...
Page 49: Table 2-2 Psr Mode Bit Values
PC, CPSR, SPSR_abt b11011 Undefined r7 to r0 r12 to r0, LR_und, SP_und, r14_und, r13_und, PC, CPSR, SPSR_und PC, CPSR, SPSR_und b11111 System r7 to r0, r14 to r0, LR, SP PC, CPSR PC, CPSR ARM720T CORE CPU MANUAL EPSON...
Page 50: Exceptions
It can also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in Thumb state when an exception occurs, it automatically switches into ARM state when the PC is loaded with the exception vector address. 2-10 EPSON ARM720T CORE CPU MANUAL...
Page 51: Table 2-3 Exception Entry And Exit
PC is the address of the instruction that was not executed because the FIQ or IRQ took priority. PC is the address of the Load or Store instruction that generated the Data Abort. The value saved in r14_svc upon reset is Unpredictable. ARM720T CORE CPU MANUAL EPSON 2-11...
Page 52 All register overwriting is prevented after an abort is indicated. This means, in particular, that r15 (always the last register to be transferred) is preserved in an aborted LDM instruction. 2-12 EPSON ARM720T CORE CPU MANUAL...
Page 53: Table 2-4 Exception Vector Addresses
0x00000004 Undefined instruction Undefined 0xFFFF0008 0x00000008 Software interrupt Supervisor 0xFFFF000C 0x0000000C Abort (prefetch) Abort 0xFFFF0010 0x00000010 Abort (data) Abort 0xFFFF0014 0x00000014 Reserved Reserved 0xFFFF0018 0x00000018 0xFFFF001C 0x0000001C The low addresses are the defaults. Note: ARM720T CORE CPU MANUAL EPSON 2-13...
Page 54 Placing Data Abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry must be added to worst-case FIQ latency calculations. 2-14 EPSON ARM720T CORE CPU MANUAL...
Page 55: Relocation Of Low Virtual Addresses By The Fcse Pid
This includes the exception vectors if they are configured to lie in the bottom of the virtual memory map. This configuration is determined by the V bit in the CP15 Control Register c1. ARM720T CORE CPU MANUAL EPSON 2-15...
Page 56: Reset
Exception vectors are located at either high or low addresses depending on the state of the V bit in CP15 register 1 (LOW = low addresses, HIGH = high addresses). Resumes execution in ARM state. 2-16 EPSON ARM720T CORE CPU MANUAL...
Page 57: Implementation-Defined Behavior Of Instructions
• STRB • STRBT • STRH • STRT. 2.11.2 Early termination On the ARM720T, early termination is defined as: MLA, MUL Signed early termination. SMULL, SMLAL Signed early termination. UMULL, UMLAL Unsigned early termination. ARM720T CORE CPU MANUAL EPSON 2-17...
Page 58 2: Programmer’s Model THIS PAGE IS BLANK. 2-18 EPSON ARM720T CORE CPU MANUAL...
Page 59: Configuration
Configuration...
Page 61: About Configuration
It can have any value. If specified for writes, writing to this location causes unpredictable behavior or change in device configuration. Should Be Zero (SBZ) When writing to this location, all bits of this field should be zero. ARM720T CORE CPU MANUAL EPSON...
Page 62: Internal Coprocessor Instructions
Should Be Zero (SBZ) • the opcode_2 and CRm fields Should Be Zero except when accessing registers 7, 8, and 13 when the specified values must be used to select the desired cache, TLB, or process identifier operations. EPSON ARM720T CORE CPU MANUAL...
Page 63: Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Figure 3-3 ID Register write format ARM720T CORE CPU MANUAL EPSON...
Page 64: Figure 3-4 Control Register Read Format
When read, returns 1. When written, is ignored. B Bit 7 Big-endian/little-endian: 0 = Little-endian operation 1 = Big-endian operation. S Bit 8 System protection: Modifies the MMU protection system. R Bit 9 ROM protection: Modifies the MMU protection system. EPSON ARM720T CORE CPU MANUAL...
Page 65: Figure 3-6 Translation Table Base Register Format
[31:14] of the written value. Bits [13:0] Should Be Zero. The CRm and opcode_2 fields Should Be Zero when writing CP15 Register 2. Translation Table Base Register format is shown in Figure 3-6. 14 13 Translation base table UNP/SBZ Figure 3-6 Translation Table Base Register format ARM720T CORE CPU MANUAL EPSON...
Page 66: Figure 3-7 Domain Access Control Register Format
The CRm and opcode_2 fields Should Be Zero when reading or writing CP15 Register 5. Fault Status Register format is shown in Figure 3-8. 31 30 09 08 07 06 04 03 UNP/SBZ Domain Status Figure 3-8 Fault Status Register format EPSON ARM720T CORE CPU MANUAL...
Page 67: Figure 3-9 Fault Address Register Format
MCR p15, 0, <Rd>, c8, c7, 0 Invalidate TLB b001 b1000 Modified Virtual MCR p15, 0, <Rd>, c8, c5, 1 single entry Address MCR p15, 0, <Rd>, c8, c6, 1 MCR p15, 0, <Rd>, c8, c7, 1 ARM720T CORE CPU MANUAL EPSON...
Page 68: Figure 3-10 Fcsce Pid Register Format
PROCID Register with opcode_2 set to 1. PROCID Register format is shown in Figure 3-11. Trace PROCID Figure 3-11 PROCID Register format The PROCIDWR signal is exported to notify the ETM7 that the Trace PROCID has been written. EPSON ARM720T CORE CPU MANUAL...
Page 69 Register 14, reserved Accessing this register is undefined. Writing to Register 14 is Undefined. 3.3.11 Test Register The CP15 Register 15 is used for device-specific test operations. For more information, see Test Support Chapter 11 ARM720T CORE CPU MANUAL EPSON...
Page 70 3: Configuration THIS PAGE IS BLANK. 3-10 EPSON ARM720T CORE CPU MANUAL...
Page 71: Instruction And Data Cache
Instruction and Data Cache...
Page 73: About The Instruction And Data Cache
Memory aborts are not supported on cache line fetches and are ignored. Note: Uncachable reads (C=0) An external memory access is performed and the cache is not written. ARM720T CORE CPU MANUAL EPSON...
Page 74: Idc Validity
Enable the IDC by setting bit 2 in the Control Register. The MMU and IDC can be enabled simultaneously with a single write to the Control Register. To disable the IDC: Clear bit 2 in the Control Register. Perform a flush by writing to the cache operations register. EPSON ARM720T CORE CPU MANUAL...
Page 75: Write Buffer
Write Buffer...
Page 77: About The Write Buffer
This bit controls whether a write operation uses or does not use the write buffer. Typically, main memory is bufferable and I/O space unbufferable. The B bit can be configured for both pages and sections. ARM720T CORE CPU MANUAL EPSON...
Page 78: Write Buffer Operation
For this reason, buffered STM accesses could be less efficient than unbuffered STM accesses. You are advised to disable the write buffer (by clearing bit 3 in CP15 register 1) before moving large blocks of data. EPSON ARM720T CORE CPU MANUAL...
Page 79: The Bus Interface
The Bus Interface...
Page 81: About The Bus Interface
A write data bus is used to move data from the master to a slave. A read data bus is used to move data from a slave to the master. ARM720T CORE CPU MANUAL EPSON...
Page 82: Figure 6-1 Simple Ahb Transfer
Address and control signals For more information, see on page 6-7. AMBA Specification (Rev For a complete description of the AHB transfer mechanism, see the 2.0) EPSON ARM720T CORE CPU MANUAL...
Page 83: Bus Interface Signals
6-13. Each of these signal groups shares a common timing relationship to the bus interface cycle. All signals in the ARM720T processor bus interface are generated from or sampled by the rising edge of HCLK. ARM720T CORE CPU MANUAL EPSON...
Page 84: Figure 6-2 Ahb Bus Master Interface
HTRANS[1:0] Transf er type Transf er response HRESP[1:0] HADDR[31:0] Reset HRESETn HWRITE A HB master A ddress HSIZE[2:0] and control HCLK HBURST[2:0] Clock HCLKEN HPROT[3:0] Data HRDATA[31:0] HWDATA[31:0] Data Figure 6-2 AHB bus master interface EPSON ARM720T CORE CPU MANUAL...
Page 85: Transfer Types
(either 4, 8, or 16). The control information is identical to the previous transfer. AMBA Specification (Rev 2.0) In the , HTRANS[1:0] = b01 indicates a BUSY cycle, Note: but these are never inserted by the ARM720T processor. ARM720T CORE CPU MANUAL EPSON...
Page 86: Figure 6-4 Transfer Type Examples
The master performs the third transfer of the burst immediately, but this time the slave is unable to complete and uses HREADY to insert a single wait state. • The final transfer of the burst completes with zero wait states. EPSON ARM720T CORE CPU MANUAL...
Page 87: Address And Control Signals
Table 6-2 Transfer size encodings HSIZE[2:0] Size Transfer width b000 8 bits Byte b001 16 bits Halfword b010 32 bits Word ARM720T CORE CPU MANUAL EPSON...
Page 88: Table 6-3 Burst Type Encodings
User access Privileged access Not bufferable Bufferable Not cachable Cachable Some bus masters are not capable of generating accurate protection information, so it is recommended that slaves do not use the HPROT[3:0] signals unless strictly necessary. EPSON ARM720T CORE CPU MANUAL...
Page 89: Slave Transfer Response Signals
To prevent any single access locking the bus for a large number of clock cycles, it is recommended that slaves do not insert more than 16 wait states. ARM720T CORE CPU MANUAL EPSON...
Page 90: Data Buses
• For halfword transfers, for example 0x1234, HWDATA[31:0] is driven with the value 0x12341234, regardless of endianness. • For byte transfers, for example 0x12, HWDATA[31:0] is driven with the value 0x12121212, regardless of endianness. 6-10 EPSON ARM720T CORE CPU MANUAL...
Page 91: Table 6-6 Active Byte Lanes For A 32-Bit Little-Endian Data Bus
Table 6-6 shows active byte lanes for little-endian systems. Table 6-6 Active byte lanes for a 32-bit little-endian data bus Address Transfer size DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] offset Word Halfword Halfword Byte Byte Byte Byte ARM720T CORE CPU MANUAL EPSON 6-11...
Page 92: Arbitration
SPLIT transfers. A master gains ownership of the address bus when HGRANT is HIGH and HREADY is HIGH at the rising edge of HCLK. 6-12 EPSON ARM720T CORE CPU MANUAL...
Page 93: Bus Clocking
During reset, all masters must ensure the following: • the address and control signals are at valid levels • HTRANS[1:0] indicates IDLE. HRESETn is the only active LOW signal in the AMBA AHB specification. ARM720T CORE CPU MANUAL EPSON 6-13...
Page 94 6: The Bus Interface THIS PAGE IS BLANK. 6-14 EPSON ARM720T CORE CPU MANUAL...
Page 95: Memory Management Unit
Memory Management Unit...
Page 97: About The Mmu
64-entry TLB • hardware page table walks • round-robin replacement algorithm (also called cyclic) • invalidate whole TLB, using CP15 Register 8 Modified Virtual Address • invalidate TLB entry, selected by (MVA), using CP15 Register 8. ARM720T CORE CPU MANUAL EPSON...
Page 98: Access Permissions And Domains
The entry to be written is chosen by cycling sequentially through the TLB locations. When the MMU is turned off, as happens on reset, no address mapping occurs and all regions are marked as noncachable and nonbufferable. EPSON ARM720T CORE CPU MANUAL...
Page 99: Mmu Program-Accessible Registers
MMU during all aborts. Writing to register c8 causes the MMU to perform a TLB operation, to manipulate TLB entries. This register cannot be read. Configuration CP15 is described in Chapter 3 , with details of register formats and the coprocessor instructions you can use to access them. ARM720T CORE CPU MANUAL EPSON...
Page 100: Address Translation
Translation Table Base Register are set to zero on a read, and the table must reside on a 16KB boundary. Figure 7-1 shows the format of the Translation Table Base Register. 14 13 Translation table base Figure 7-1 Translation Table Base Register EPSON ARM720T CORE CPU MANUAL...
Page 101: Figure 7-2 Translating Page Tables
4 KB Fine page table base Invalid Indexed by modified virtual address bits [19:10] Tiny page Tiny page base Indexed by modified 1024 entries virtual address bits [9:0] 1 KB Figure 7-2 Translating page tables ARM720T CORE CPU MANUAL EPSON...
Page 102: Figure 7-3 Accessing Translation Table Level One Descriptors
There are two sizes of page table: • coarse page tables have 256 entries, splitting the 1MB that the table describes into 4KB blocks • fine page tables have 1024 entries, splitting the 1MB that the table describes into 1KB blocks. EPSON ARM720T CORE CPU MANUAL...
Page 103: Table 7-2 Level One Descriptor Bits
Generates a section translation fault Coarse page Indicates that this is a coarse page table table descriptor Section Indicates that this is a section descriptor Fine page table Indicates that this is a fine page table descriptor ARM720T CORE CPU MANUAL EPSON...
Page 104: Figure 7-5 Section Descriptor
5 4 3 2 1 0 Coarse page table base address Domain Figure 7-6 Coarse page table descriptor If a coarse page table descriptor is returned from the level one fetch, a level two Note: fetch is initiated. EPSON ARM720T CORE CPU MANUAL...
Page 105: Figure 7-7 Fine Page Table Descriptor
These bits specify one of the 16 possible domains (held in the Domain Access Control Registers) that contain the primary access controls Always written as 1 Always written as 0 These bits must be b11 to indicate a fine page table descriptor ARM720T CORE CPU MANUAL EPSON...
Page 106: Figure 7-8 Section Translation
5 4 3 2 1 0 Fault Large page Large page base address Small page Small page base address C B 1 0 Tiny page Tiny page base address Figure 7-9 Level two descriptor 7-10 EPSON ARM720T CORE CPU MANUAL...
Page 107: Table 7-7 Level Two Descriptor Bits
Indicates that this is a 4KB page Tiny page Indicates that this is a 1KB page Tiny pages do not support subpage permissions and therefore only have one set of Note: access permission bits. ARM720T CORE CPU MANUAL EPSON 7-11...
Page 108: Figure 7-10 Large Page Translation From A Coarse Page Table
If a large page descriptor is included in a fine page table, the high-order six bits of the page index and low-order six bits of the fine page table index overlap. Each fine page table entry for a large page must therefore be duplicated 64 times. 7-12 EPSON ARM720T CORE CPU MANUAL...
Page 109: Figure 7-11 Small Page Translation From A Coarse Page Table
If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must therefore be duplicated four times. ARM720T CORE CPU MANUAL EPSON 7-13...
Page 110: Figure 7-12 Tiny Page Translation From A Fine Page Table
TLB if the subpage permission differs, and a 64KB entry is put in the TLB if the subpage permissions are identical. When you use subpage permissions, and the page entry then has to be invalidated, you must invalidate all four subpages separately. 7-14 EPSON ARM720T CORE CPU MANUAL...
Page 111: Mmu Faults And Cpu Aborts
Fault Status Register and Fault Address Register (see Fault address and fault status registers on page 7-16). An access violation for a given memory access inhibits any corresponding external access, with an abort returned to the CPU core. ARM720T CORE CPU MANUAL EPSON 7-15...
Page 112: Fault Address And Fault Status Registers
[3:0] can occur because the fault is raised before a valid domain field has been read from a page table descriptor. Any abort masked by the priority encoding can be regenerated by fixing the primary abort and restarting the instruction. 7-16 EPSON ARM720T CORE CPU MANUAL...
Page 113: Domain Access Control
Reserved Reserved. Currently behaves like the no access mode Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated ARM720T CORE CPU MANUAL EPSON 7-17...
Page 114: Table 7-11 Interpreting Access Permission (Ap) Bits
Supervisor mode Read/write Read-only Writes in User mode cause permission fault Read/write Read/write All access types permitted in both modes Reserved Do not use this encoding. [S:R] = b11 generates a fault for any access. 7-18 EPSON ARM720T CORE CPU MANUAL...
Page 115: Fault Checking Sequence
MMU is enabled or not. An alignment fault is not generated on any instruction fetch, nor on any byte access. If the access generates an alignment fault, the access sequence aborts without Note: reference to more permission checks. ARM720T CORE CPU MANUAL EPSON 7-19...
Page 116 AP bits of the level one descriptor define whether or not the access is allowed in the same way as for a section. The fault generated is a page permission fault. 7-20 EPSON ARM720T CORE CPU MANUAL...
Page 117: External Aborts
If the MMU is enabled, then disabled and subsequently re-enabled, the contents of Note: the TLB are preserved. If these are now invalid, you must invalidate the TLB before TLB Operations Register re-enabling the MMU. See on page 3-7. ARM720T CORE CPU MANUAL EPSON 7-21...
Page 118 7: Memory Management Unit THIS PAGE IS BLANK. 7-22 EPSON ARM720T CORE CPU MANUAL...
Page 119: Coprocessor Interface
Coprocessor Interface...
Page 121: About Coprocessors
(using CPnCPI). Generates any addresses that are required by the instruction, including prefetching the next instruction to refill the pipeline. Takes the undefined instruction trap if no coprocessor accepts the instruction. ARM720T CORE CPU MANUAL EPSON...
Page 122: Table 8-1 Coprocessor Availability
Available to users Reserved If you intend to design a coprocessor, send an E-mail with coprocessor in the subject Note: line to info@arm.com for up to date information on coprocessor numbers that have already been allocated. EPSON ARM720T CORE CPU MANUAL...
Page 123: Coprocessor Interface Signals
8-4 Coprocessor interface handshaking • on page 8-5 Connecting coprocessors • on page 8-9 Not using an external coprocessor • on page 8-10 Undefined instructions • on page 8-10 Privileged instructions • on page 8-10 ARM720T CORE CPU MANUAL EPSON...
Page 124: Pipeline-Following Signals
There are no coprocessor instructions in the Thumb instruction set, so coprocessors must monitor the state of the CPTBIT signal to ensure that they do not try to decode pairs of Thumb instructions as ARM instructions. EPSON ARM720T CORE CPU MANUAL...
Page 125: Coprocessor Interface Handshaking
A coprocessor in the system has signalled on EXTCPA and EXTCPB that it is able to accept the instruction. If all these requirements are met, the ARM720T processor signals by taking CPnCPI LOW. This commits the coprocessor to the execution of the coprocessor instruction. ARM720T CORE CPU MANUAL EPSON...
Page 126: Figure 8-1 Coprocessor Busy-Wait Sequence
The actions taken by the coprocessor must not corrupt the state of the coprocessor, and must be repeatable with identical results. The coprocessor can only change its own state after the instruction has been executed. EPSON ARM720T CORE CPU MANUAL...
Page 127: Figure 8-2 Coprocessor Register Transfer Sequence
Execute stage CPnCPI (from core) EXTCPA (from coprocessor) EXTCPB (from coprocessor) HRDATA[31:0] I Fetch I Fetch I Fetch I Fetch I Fetch I Fetch (ADD) (SUB) (CPDO) (TST) (SWINE) Figure 8-3 Coprocessor data operation sequence ARM720T CORE CPU MANUAL EPSON...
Page 128: Figure 8-4 Coprocessor Load Sequence
(from coprocessor) EXTCPB (from coprocessor) I Fetch I Fetch I Fetch I Fetch I Fetch CP data CP data CP data CP data I Fetch HRDATA[31:0] (ADD) (SUB) (CPDO) (TST) (SWINE) Figure 8-4 Coprocessor load sequence EPSON ARM720T CORE CPU MANUAL...
Page 129: Connecting Coprocessors
The individual CPA and CPB outputs from each coprocessor must be ANDed together, and connected to the EXTCPA and EXTCPB inputs on the ARM720T processor You must also multiplex the output data from the coprocessors. ARM720T CORE CPU MANUAL EPSON...
Page 130: Not Using An External Coprocessor
If a User-mode process (CPnTRANS LOW) tries to access a coprocessor instruction Note: that can only be executed in a privileged mode, the coprocessor must respond with EXTCPA and EXTCPB HIGH. This causes the ARM720T processor to take the undefined instruction trap. 8-10 EPSON ARM720T CORE CPU MANUAL...
Page 131: Debugging Your System
Debugging Your System...
Page 133 Programming breakpoints ............... 9-36 9.22 Programming watchpoints............... 9-38 9.23 Abort status register ................9-38 9.24 Debug control register................9-39 9.25 Debug status register................9-41 9.26 Coupling breakpoints and watchpoints ..........9-43 9.27 EmbeddedICE-RT timing ................ 9-44 ARM720T CORE CPU MANUAL EPSON...
Page 134: About Debugging Your System
• examine the state of the memory system • execute abort exceptions, enabling real-time monitoring of the core • resume program execution. The debug host and the protocol converter are system-dependent. EPSON ARM720T CORE CPU MANUAL...
Page 135: Controlling Debugging
These blocks are shown in Figure 9-2. ARM720T processor ARM720T EmbeddedICE-RT System control processor Scan chain 2 Scan chain 15 ARM720T TAP controller (also provides scan chain 0 control signals) Figure 9-2 ARM720T processor block diagram ARM720T CORE CPU MANUAL EPSON...
Page 136: Debug Modes
In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM720T core. Scan chains and For detailed information about the scan chains and the JTAG interface, see the JTAG interface on page 9-17. EPSON ARM720T CORE CPU MANUAL...
Page 137: Entry Into Debug State
When it enters debug state, the DBGACK signal is asserted. The timing for an externally-generated breakpoint is shown in Figure 9-3. HCLK HADDR[31:0] DATA[31:0] DBGBREAK DBGACK HTRANS[1:0] Memory cycles Internal cycles Figure 9-3 Debug state entry ARM720T CORE CPU MANUAL EPSON...
Page 138 If a watchpoint occurs when an exception is pending, the core enters debug state in the same mode as the exception. EPSON ARM720T CORE CPU MANUAL...
Page 139 HRESETn is held stable during debug. When the system applies reset to the ARM720T processor (that is, HRESETn is driven LOW), the ARM720T processor state changes with the debugger unaware that the core has reset. ARM720T CORE CPU MANUAL EPSON...
Page 140: Figure 9-4 Clock Synchronization
Reset circuit DBGTDO DBGTCKEN RTCK TCK synchronizer HCLK DBGTMS HCLK DBGTDI HCLK Input sample and hold Multi_ICE interface pads HCLK Figure 9-4 Clock synchronization All the D-types shown in Figure 9-4 are reset by DBGnTRST. Note: EPSON ARM720T CORE CPU MANUAL...
Page 141: Debug Interface
The ARM720T processor has a single clock, HCLK, that is qualified by two clock enables: • HCLKEN controls access to the memory system • DBGTCKEN controls debug operations. When the ARM720T processor is in debug state, DBGTCKEN conditions HCLK to clock the core. ARM720T CORE CPU MANUAL EPSON...
Page 142: The Embeddedice-Rt Macrocell
You can configure each watchpoint unit to be either a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be data-dependent. Watchpoint unit registers For more details, see on page 9-33. 9-10 EPSON ARM720T CORE CPU MANUAL...
Page 143: Disabling Embeddedice-Rt
9-39). Bit 5 is also known as the EmbeddedICE-RT disable bit. You must set bit 5 before doing either of the following: • programming breakpoint or watchpoint registers • changing bit 4 of the Debug Control Register. ARM720T CORE CPU MANUAL EPSON 9-11...
Page 144: Embeddedice-Rt Register Map
Prefetch or Data Abort vectors respectively. Bit 4 clear Monitor mode debugging is disabled and the system is placed into halt mode. In halt mode, the core enters debug state when it encounters a breakpoint or watchpoint. 9-12 EPSON ARM720T CORE CPU MANUAL...
Page 145 Change the other registers. Re-enable the watchpoint unit by clearing the EmbeddedICE-RT disable bit in the Debug Control Register. Debug control register on page 9-39 for more information about controlling core behavior at breakpoints and watchpoints. ARM720T CORE CPU MANUAL EPSON 9-13...
Page 146: The Debug Communications Channel
The Domain Access Control Register is read-only and enables synchronized handshaking between the processor and the debugger. The register format is shown in Figure 9-6. 28 27 2 1 0 EmbeddedICE-RT version number Figure 9-6 Domain Access Control Register 9-14 EPSON ARM720T CORE CPU MANUAL...
Page 147: Table 9-2 Domain Access Control Register Bit Assignments
Returns the value from the DCC data read register into the destination register Rd. The Thumb instruction set does not contain coprocessor instructions, so it is Note: recommended that these are accessed using SWI instructions when in Thumb state. ARM720T CORE CPU MANUAL EPSON 9-15...
Page 148 14. The action of this load clears the R bit in the debug comms control register. If the R bit is clear, this indicates that the data has been taken and the process can now be repeated. 9-16 EPSON ARM720T CORE CPU MANUAL...
Page 149: Scan Chains And The Jtag Interface
0 through 31 • the DBGBREAK bit (the first to be shifted out). Scan chain 2 Test data registers Scan chain 2 enables access to the EmbeddedICE-RT registers. See on page 9-22 for details. ARM720T CORE CPU MANUAL EPSON 9-17...
Page 150: Table 9-3 Instruction Encodings For Scan Chain 15
Instruction register (described in on page 9-23). The loading of instructions is controlled by the Test Access Port (TAP) controller. The TAP controller For more information about the TAP controller, see on page 9-19. 9-18 EPSON ARM720T CORE CPU MANUAL...
Page 151: The Tap Controller
The IDCODE instruction is selected. When the TAP controller is put into the SHIFT-DR state and HCLK is pulsed while enabled by DBGTCKEN, the contents of the ID register are clocked out of DBGTDO. ARM720T CORE CPU MANUAL EPSON 9-19...
Page 152: Public Jtag Instructions
In the SHIFT-DR state, the previously-captured test data is shifted out of the scan chain through the DBGTDO pin, while new test data is shifted in through the DBGTDI pin. Single-step operation of the core is possible using the INTEST instruction. 9-20 EPSON ARM720T CORE CPU MANUAL...
Page 153 DBGTDI and DBGTDO. The TAP controller behaves as if the BYPASS instruction had been loaded. The processor exits debug state when the RUN-TEST/IDLE state is entered. Exit from debug state For more information, see on page 9-29. ARM720T CORE CPU MANUAL EPSON 9-21...
Page 154: Test Data Registers
DBGTDI and DBGTDO. There is no parallel output from the ID register. The 32-bit device identification code is loaded into the ID register from its parallel inputs during the CAPTURE-DR state. 9-22 EPSON ARM720T CORE CPU MANUAL...
Page 155: Table 9-5 Scan Chain Number Allocation
0 is selected as the active scan chain. Table 9-5 shows the scan chain number allocation. Table 9-5 Scan chain number allocation Scan chain number Function (User-implemented) Debug EmbeddedICE-RT programming Reserved Reserved Reserved When selected, reserved scan chains scan out zeros. ARM720T CORE CPU MANUAL EPSON 9-23...
Page 156 Length 38 bits. Scan chain order From DBGTDI to DBGTDO, the read/write bit, the register address bits, bits 4 to 0, then the data bits, bits 0 to 31. No action occurs during CAPTURE-DR. 9-24 EPSON ARM720T CORE CPU MANUAL...
Page 157: Scan Timing
Table 9-6 Scan chain 1 cells Number Signal Type DATA[0] Input/output DATA[1] Input/output DATA[2] Input/output DATA[3] Input/output DATA[4] Input/output DATA[5] Input/output DATA[6] Input/output DATA[7] Input/output DATA[8] Input/output DATA[9] Input/output DATA[10] Input/output DATA[11] Input/output DATA[12] Input/output DATA[13] Input/output ARM720T CORE CPU MANUAL EPSON 9-25...
Page 158: Examining The Core And The System In Debug State
Thumb state or ARM state, by examining bit 4 of the EmbeddedICE-RT debug status register, as follows: Bit 4 HIGH The core has entered debug from Thumb state. Bit 4 LOW The core has entered debug from ARM state. 9-26 EPSON ARM720T CORE CPU MANUAL...
Page 159 ; Enter USER mode STM R0, {r13,r14} ; Save register not previously visible ORR R0, 0x01 ; Select FIQ mode MSR CPSR, R0 ; Enter FIQ mode STM R0, {r8-r14} ; Save banked FIQ registers ARM720T CORE CPU MANUAL EPSON 9-27...
Page 160 There are restrictions on which instructions can have bit 33 set. The valid instructions on which to set this bit are: • loads • stores • load multiple • store multiple. Exit from debug state See also on page 9-29. 9-28 EPSON ARM720T CORE CPU MANUAL...
Page 161: Exit From Debug State
Figure 9-11 shows the behavior of the ARM720T processor on exit from the debug state. HCLK HTRANS Internal cycles HADDR[31:0] Ab+4 Ab+8 DATA[31:0] DBGACK Figure 9-11 Debug exit sequence ARM720T CORE CPU MANUAL EPSON 9-29...
Page 162: The Program Counter During Debug
Debug entry adds four addresses to the PC, and every instruction adds one address. The difference from breakpoint is that the instruction that caused the watchpoint has executed, and the program must return to the next instruction. 9-30 EPSON ARM720T CORE CPU MANUAL...
Page 163 In this case, the value of the PC is invalid, but because the debugger can determine which location was being accessed, the debugger can be written to help the abort handler fix the memory system. ARM720T CORE CPU MANUAL EPSON 9-31...
Page 164: Priorities And Exceptions
This time, when the instruction is fetched, and providing the breakpoint is activated (it can be data-dependent), the ARM720T processor enters debug state. The Prefetch Abort, therefore, takes higher priority than the breakpoint. 9-32 EPSON ARM720T CORE CPU MANUAL...
Page 165: Watchpoint Unit Registers
A watchpoint register is programmed by shifting data into the EmbeddedICE-RT scan chain (scan chain 2). The scan chain is a 38-bit shift register comprising: • a 32-bit data field • a 5-bit address field • a read/write bit. This setup is shown in Figure 9-12. ARM720T CORE CPU MANUAL EPSON 9-33...
Page 166: Figure 9-12 Embeddedice-Rt Block Diagram
The 32-bit data field is ignored. The register addresses are shown in Table 9-1 on page 9-12. A read or write takes place when the TAP controller enters the UPDATE-DR state. Note: 9-34 EPSON ARM720T CORE CPU MANUAL...
Page 167: Figure 9-13 Watchpoint Control Value, And Mask Format
(PROT[0] = 0), or a data access (PROT[0] = 1). PROT[1] Is used to compare against the not translate signal from the core in order to distinguish between user mode (PROT[1] = 0), and non-User mode (PROT[1] = 1) accesses. ARM720T CORE CPU MANUAL EPSON 9-35...
Page 168: Programming Breakpoints
Program the breakpoint bits for each state as follows: For an ARM state breakpoint Set bits [1:0] of the address mask register. For a Thumb state breakpoint Set bit 0 of the address mask register. In either case, clear the remaining bits. 9-36 EPSON ARM720T CORE CPU MANUAL...
Page 169 Read the instruction at the desired address and store it. Write the special bit pattern representing a software breakpoint at the address. Clearing the breakpoint To clear the software breakpoint, restore the instruction to the address. ARM720T CORE CPU MANUAL EPSON 9-37...
Page 170: Programming Watchpoints
Abort signal are asserted, the external Abort takes priority, and the DbgAbt bit is not set. Once set, DbgAbt remains set until reset by the user. The register is accessed by MRC and MCR instructions. 9-38 EPSON ARM720T CORE CPU MANUAL...
Page 171: Debug Control Register
If set, the interrupt enable signal of the core (IFEN) is forced LOW. The IFEN signal is driven as shown in Table 9-10. • If clear, interrupts are enabled. Used to force the value on DBGRQ. Used to force the value on DBGACK. ARM720T CORE CPU MANUAL EPSON 9-39...
Page 172: Table 9-10 Interrupt Signal Control
DBGACK seen at the periphery of the ARM720T core. This enables the debug system to signal to the rest of the system that the core is still being debugged even when system-speed accesses are being performed (when the internal DBGACK signal from the core is LOW). 9-40 EPSON ARM720T CORE CPU MANUAL...
Page 173: Debug Status Register
Enables the state of the core interrupt enable signal, IFEN, to be read. Enables the values on the synchronized version of DBGRQ to be read. Enables the values on the synchronized versions of DBGACK to be read. ARM720T CORE CPU MANUAL EPSON 9-41...
Page 174: Figure 9-17 Debug Control And Status Register Structure
Bit 2 Bit 2 Bit 1 DBGRQI (to core) DBGRQ Bit 1 (from ARM720T input) Bit 0 DBGACK (to ARM720T processor output) DBGACKI Bit 0 (from core) Figure 9-17 Debug control and status register structure 9-42 EPSON ARM720T CORE CPU MANUAL...
Page 175: Coupling Breakpoints And Watchpoints
The output of the latch drives the CHAIN input of the breakpoint comparator. The address YYY is stored in the breakpoint register, and when the CHAIN input is asserted, the breakpoint address matches and the breakpoint triggers correctly. ARM720T CORE CPU MANUAL EPSON 9-43...
Page 176: Embeddedice-Rt Timing
If Watchpoint 0 matches but Watchpoint 1 does not (that is, the RANGE input to Watchpoint 0 is 0), the breakpoint is triggered. 9.27 EmbeddedICE-RT timing EmbeddedICE-RT samples the DBGEXT[1] and DBGEXT[0] inputs on the rising edge of HCLK. 9-44 EPSON ARM720T CORE CPU MANUAL...
Page 177: Etm Interface
ETM Interface...
Page 179: About The Etm Interface
ETMEN input is LOW, all the output pins of the ETM interface remain stable. You can control this ETMEN input by connecting it with either of the following: • the ETMEN output on the ETM7 • the inverted PWRDOWN output on the ETM7. ARM720T CORE CPU MANUAL EPSON 10-1...
Page 180: Connections Between The Etm7 Macrocell And The Arm720T Processor
MAS[1:0] ETMSIZE[1:0] nCPI ETMnCPI nEXEC ETMnEXEC nOPC ETMnOPC nRESET HRESETn ETMnRW nTRST DBGnTRST PROCID[31:0] ETMPROCID[31:0] PROCIDWR ETMPROCIDWR ETMEN or inverted PWRDOWN ETMEN ETMHIVECS RANGEOUT[0] DBGRNG[0] RANGEOUT[1] DBGRNG[1] RDATA[31:0] ETMRDATA[31:0] TBIT ETMTBIT HCLK TCKEN DBGTCKEN 10-2 EPSON ARM720T CORE CPU MANUAL...
Page 181: Clocks And Resets
The ARM720T processor does not provide a scan chain expansion input. ARM Limited recommends that you connect the ARM720T processor and the ETM7 TAP controllers in ETM7 (Rev 1) Technical Reference Manual parallel. For more details, see the ARM720T CORE CPU MANUAL EPSON 10-3...
Page 182 10: ETM Interface THIS PAGE IS BLANK. 10-4 EPSON ARM720T CORE CPU MANUAL...
Page 183: Test Support
Test Support...
Page 185: About The Arm720T Test Registers
R S B L D P W C A M Figure 11-1 CP15 MRC and MCR bit pattern The L bit distinguishes between an MCR (L set to 1) and an MRC (L set to 0). ARM720T CORE CPU MANUAL EPSON 11-1...
Page 186: Automatic Test Pattern Generation (Atpg)
In addition to the auto-inserted scan chains, the ARM720T processor includes all the signals for an optional INTEST/EXTEST scan chain, scan chain 0. ATPG Seven balanced scan chains are provided for ATPG, along with a test enable and a single scan enable. 11-2 EPSON ARM720T CORE CPU MANUAL...
Page 187: Test State Register
The register c15 operations are all issued as MCR. The Rd field defines the address for the operation. Therefore, the data is either supplied from, or latched into, CP15.C in CP15. These 32-bit registers are accessed with CP15 MCR and MRC instructions. ARM720T CORE CPU MANUAL EPSON 11-3...
Page 188: Figure 11-2 Rd Format, Cam Read
7 6 5 4 MVA TAG Figure 11-3 Rd format, CAM write In Figure 11-3, bit labels have the following meanings: Valid. Dirty even (words [3:0]). Not used. Dirty odd (words [7:4]). Not used. Writeback. Not used. 11-4 EPSON ARM720T CORE CPU MANUAL...
Page 189: Figure 11-4 Rd Format, Ram Read
7 6 5 4 MVA TAG LFSR[6] Figure 11-7 Data format, CAM read The RAM read format for data is shown in Figure 11-8. RAM data word [31:0] Figure 11-8 Data format, RAM read ARM720T CORE CPU MANUAL EPSON 11-5...
Page 190: Figure 11-9 Data Format, Cam Match Ram Read
MCR CAM read is executed. This is intended for use in debug to establish the value of the current victim pointer of each segment before reading the values of the CAM and RAM, so that the value can be restored afterwards. 11-6 EPSON ARM720T CORE CPU MANUAL...
Page 191 ; Write pattern 0x5A5A5A5A in RAM line (eight words) LDR r0,=0x5A5A5A5A MOV r8,#8 MOV r2,#0x10 ;write segment 1,word 0 MCR p15,3,r0,c15,c3,0 ; write RAM data in C15.C loop0 MCR p15,2,r2,c15,c11,6 ; write RAM ADD r2,r2,#0x04 ; next word SUBS r8,r8,#1 BNE loop0 ARM720T CORE CPU MANUAL EPSON 11-7...
Page 192: Mmu Test Registers And Operations
TLB • invalidate single entry using MVA. The CP15 register c10 operations control TLB lockdown. These operations are: • read victim, lockdown base and preserve bit • write victim, lockdown base and preserve bit. 11-8 EPSON ARM720T CORE CPU MANUAL...
Page 193: Table 11-5 Cam, Ram1, And Ram2 Register C15 Operations
CAM read to C15.M MCR p15, 4, <Rd>, c15, c7, 4 CAM write Tag, Size, V, P MCR p15, 4, <Rd>, c15, c7, 0 RAM1 read to C15.M MCR p15, 4, <Rd>, c15, c11, 4 ARM720T CORE CPU MANUAL EPSON 11-9...
Page 194: Figure 11-12 Rd Format, Cam Write And Data Format, Cam Read
Memory region size b1111 b0111 64KB b0011 16KB b0001 b0000 Figure 11-13 shows the format of Rd for RAM1 writes. 22 21 6 5 4 DOMAIN (one hot encoding) Figure 11-13 Rd format, RAM1 write 11-10 EPSON ARM720T CORE CPU MANUAL...
Page 195: Figure 11-14 Data Format, Ram1 Read
TLB miss Figure 11-15 shows the Rd format for RAM2 writes, and the data format for RAM2 reads. 25 24 FCSE PID UNP/SBZ Figure 11-15 Rd format, RAM2 write and data format, RAM2 read ARM720T CORE CPU MANUAL EPSON 11-11...
Page 196: Figure 11-16 Rd Format, Write Tlb Lockdown
The write TLB lockdown operation is: MCR p15, 0, <Rd>, c10, c0, 0 The write TLB lockdown format for Rd is shown in Figure 11-16. 20 19 Base Victim Figure 11-16 Rd format, write TLB lockdown 11-12 EPSON ARM720T CORE CPU MANUAL...
Page 197 ; read RAM1 to R6 BIC r5,r5,#0x01c00000 ; mask fault/miss bits MCR p15,4,r7,c15,c3,5 MRC p15,4,r7,c15,c3,6 ; read RAM2 to R7 CMP r5,r2 CMPEQ r6,r3 CMPEQ r7,r4 BNE TEST_FAIL SUBS r8,r8,#1 BNE loop1 B TEST_PASS ARM720T CORE CPU MANUAL EPSON 11-13...
Page 198 11: Test Support THIS PAGE IS BLANK. 11-14 EPSON ARM720T CORE CPU MANUAL...
Page 199 Appendix A Signal Descriptions...
Page 201: A Signal Descriptions
Indicates that the current transfer has finished. HRESP[1:0] Input Indicates transfer status. HWDATA[31:0] Output Write data bus. HRDATA[31:0] Input Read data bus. HBUSREQ Output Bus transfer request. HLOCK Output Indicates locked access. HCLKEN Input Bus clock enable. HRESETn Input Global reset. ARM720T CORE CPU MANUAL EPSON...
Page 202: Coprocessor Interface Signals
External coprocessor data bus enable. This signal when HIGH, indicates that the coprocessor intends to drive the coprocessor data bus, CPDATA. If the coprocessor interface is not to be used then this signal must be tied LOW. EPSON ARM720T CORE CPU MANUAL...
Page 203: Jtag And Test Signals
EXTEST state signal. DBGnTDOEN Output Test data out enable. DBGnTRST Input Not test reset. When LOW, this signal resets the JTAG interface. DBGTCKEN Input Test clock enable. DBGTDI Input Test data in. JTAG test data in signal. ARM720T CORE CPU MANUAL EPSON...
Page 204: Debugger Signals
In most systems, this input is tied LOW. DBGRQ must be deasserted on the same clock that DBGACK is asserted. DBGEXT[1:0] Input External condition. These signals allow breakpoints and watchpoints to depend on an external condition. EPSON ARM720T CORE CPU MANUAL...
Page 205: Embedded Trace Macrocell Interface Signals
The coprocessor busy signal. It is a buffered version of the coprocessor absent signal. ETMPROCID[31:0] Output Trace PROCID bus. ETMPROCIDWR Output Trace PROCID write. Indicates to the ETM7 that the Trace PROCID, CP15 register c13, has been written. ARM720T CORE CPU MANUAL EPSON...
Page 206 LOW, indicates a processor read cycle. ETMCLKEN Output This signal is used to indicate to the ETM that the core is in a wait state. It is not a true clock enable for the ETM. EPSON ARM720T CORE CPU MANUAL...
Page 207: Atpg Test Signals
Determines the state of the V bit in CP15 register c1 at reset. When HIGH, the V bit is set coming out of rest. When LOW, the V bit is clear coming out of reset. ARM720T CORE CPU MANUAL EPSON...
Page 208 A: Signal Descriptions THIS PAGE IS BLANK. EPSON ARM720T CORE CPU MANUAL...
Page 209 Glossary...
Page 211 The banked registers are registers r8 to r14, or r13 to r14, depending on the processor mode. A location in the program. If execution reaches this location, the debugger Breakpoint halts execution of the code image. See also Watchpoint. Complex Instruction Set Computer. CISC ARM720T CORE CPU MANUAL EPSON Glossary-1...
Page 212 Privileged modes that are entered when specific exceptions occur. Handles an event. For example, an exception could handle an external Exception interrupt or an undefined instruction. An abort that is generated by the external memory system. External abort Fast interrupt. Glossary-2 EPSON ARM720T CORE CPU MANUAL...
Page 213 (such as an ARM7TDMI-S core, an ETM7, and a memory block) plus application-specific logic. Memory Management Unit Allows control of a memory system. Most of the control is provided through translation tables held in memory. Memory Management Unit ARM720T CORE CPU MANUAL EPSON Glossary-3...
Page 214 • they require fewer transistors, this makes them cheaper to produce and more power efficient. See also Complex Instruction Set Computer. Reduced Instruction Set Computer RISC Glossary-4 EPSON ARM720T CORE CPU MANUAL...
Page 215 SP points to the most recently pushed item, else if the stack is empty, the SP points to the first empty location, where the next item will be pushed. Program Status Register. Status registers Stack pointer Software Interrupt Instruction. Test access port ARM720T CORE CPU MANUAL EPSON Glossary-5...
Page 216 Do not contain valid data, and a value can vary from moment to moment, instruction to instruction, and implementation to implementation. A location in the image that is monitored. If the value stored there changes, Watchpoint the debugger halts execution of the image. See also Breakpoint. Glossary-6 EPSON ARM720T CORE CPU MANUAL...
Page 217 Index...
Page 219 8-5 Descriptor chain cells 9-19 interface handshaking 8-5 coarse page table 7-8 interface 9-19 interface signals 8-3, A-2 fine page table 7-9 Breakpoint load and store operations 8-8 level one 7-6 address mask 9-37 ARM DDI 0229B EPSON Index-1...
Page 220 9-20, 9-21, 9-22, 9-23 Miscellaneous signals A-7 Instruction set 1-5 MMU 7-1 ARM 1-7 enabling 3-5 Thumb 1-14 enabling and disabling 7-21 FAR 7-16 Instruction types 1-5 faults 7-15 Fast Context Switch Extension Interface registers 7-3 Index-2 EPSON ARM DDI 0229B...
Page 221 9-22 test 11-1 Response encoding 6-10 UPDATE-DR 9-20, 9-21 test state 11-3 RESTART UPDATE-IR 9-23 translation table base 7-4 on exit from debug 9-21 Subpages 7-14 Registers 3-3 RESTART instruction 9-21, 9-28, Supervisor mode 2-4 ARM DDI 0229B EPSON Index-3...
Page 222 User mode 2-4 Watchpoint 9-5, 9-6, 9-10, 9-24, 9-30, 9-43 aborted 9-31 coupling 9-43 EmbeddedICE-RT 9-36 externally generated 9-5 programming 9-38 register 9-33, 9-37 registers 9-33 programming and reading 9-33 unit 9-38 with exception 9-32 Index-4 EPSON ARM DDI 0229B...
Page 223 Phone: +852-2585-4600 Fax: +852-2827-4346 Phone: +1-815-455-7630 Fax: +1-815-455-7633 Telex: 65542 EPSCO HX Northeast 301 Edgewater Place, Suite 120 EPSON TAIWAN TECHNOLOGY & TRADING LTD. Wakeﬁeld, MA 01880, U.S.A. 14F, No. 7, Song Ren Road, Phone: +1-781-246-3600 Fax: +1-781-246-5443 Taipei 110 Southeast...
Page 224 ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Document code: 405003400 Issue April, 2004 Printed in Japan...

Epson ARM720T Core Cpu Manual

1 Introduction

2 Programmer's Model

3 Configuration

4 Instruction and Data Cache

5 Write Buffer

6 The Bus Interface

7 Memory Management Unit

8 Coprocessor Interface

9 Debugging Your System

10 ETM Interface

11 Test Support

A Signal Descriptions

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