Figure 8-2 Coprocessor Register Transfer Sequence; Figure 8-3 Coprocessor Data Operation Sequence - Epson ARM720T Core Cpu Manual

8.4.5 Coprocessor register transfer instructions
The coprocessor register transfer instructions, MCR and MRC, transfer data between a
register in the ARM720T processor register bank and a register in the coprocessor register
bank. An example sequence for a coprocessor register transfer is shown in Figure 8-2.
HCLK
Fetch stage
Decode stage
Execute stage
CPnCPI
(from core)
EXTCPA (from
coprocessor)
EXTCPB (from
coprocessor)
HRDATA[31:0]
HWDATA[31:0]
8.4.6 Coprocessor data operations
The coprocessor data processing instructions, CDP, perform processing operations on the data
held in the coprocessor register bank. No information is transferred between the ARM720T
core and the coprocessor as a result of this operation. An example sequence is shown in
Figure 8-3.
Fetch stage
Decode stage
Execute stage
CPnCPI
(from core)
EXTCPA (from
coprocessor)
EXTCPB (from
coprocessor)
HRDATA[31:0]
ARM720T CORE CPU MANUAL
ADD SUB MCR
ADD SUB
ADD
I Fetch I Fetch
(ADD) (SUB)

Figure 8-2 Coprocessor register transfer sequence

HCLK
ADD SUB
ADD
I Fetch I Fetch
(ADD) (SUB)

Figure 8-3 Coprocessor data operation sequence

TST SWINE
MCR TST
SUB MCR
I Fetch I Fetch I Fetch
(MCR) (TST) (SWINE)
Tx
A
CPDO TST SWINE
SUB CPDO TST SWINE
ADD SUB CPDO TST
I Fetch I Fetch I Fetch
(CPDO) (TST) (SWINE)
EPSON
8: Coprocessor Interface
SWINE
TST SWINE
I Fetch
C
SWINE
I Fetch
8-7