Bus Interface Signals; The Bus Interface - Epson ARM720T Core Cpu Manual

6.2

Bus interface signals

The signals in the ARM720T processor bus interface can be grouped into the following
categories:
Transfer type
Address and control
Slave transfer response
Data
Arbitration
Clock
Reset
Each of these signal groups shares a common timing relationship to the bus interface cycle.
All signals in the ARM720T processor bus interface are generated from or sampled by the
rising edge of HCLK.
ARM720T CORE CPU MANUAL
HTRANS[1:0]
Transfer types
See on page 6-5.
HADDR[31:0]
HWRITE
HSIZE[2:0]
HBURST[2:0]
HPROT[3:0]
Address and control signals
See
HREADY
HRESP[1:0]
Slave transfer response signals
See
HRDATA[31:0]
HWDATA[31:0]
Data buses
See on page 6-10.
HBUSREQ
HGRANT
HLOCK
Arbitration
See on page 6-12.
HCLK
HCLKEN
Bus clocking
See on page 6-13.
HRESETn
Reset
See on page 6-13.
EPSON

6: The Bus Interface

on page 6-7.
on page 6-9.
6-3