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9.3.3
Entry into debug state on debug request
An ARM720T core in halt mode can be forced into debug state on debug request in either of
the following ways:
•
through EmbeddedICE-RT programming (see
Programming watchpoints
9-36, and
•
by asserting the DBGRQ pin.
DBGRQ must be deasserted on the same clock that DBGACK is asserted.
When the DBGRQ pin has been asserted, the core normally enters debug state at the end of
the current instruction. However, when the current instruction is a busy-waiting access to a
coprocessor, the instruction terminates, and the ARM720T core enters debug state
immediately. This is similar to the action of nIRQ and nFIQ.
9.3.4
Action of the ARM720T processor in debug state
When the ARM720T processor enters debug state, the core forces HTRANS[1:0] to indicate
internal cycles. This action enables the rest of the memory system to ignore the ARM720T core
and to function as normal. Because the rest of the system continues to operate, the ARM720T
core is forced to ignore aborts and interrupts.
Caution: Do not reset the core while debugging, otherwise the debugger loses track of the
core.
The system must not change the ETMBIGEND signal during debug. From the
Note:
point of view of the programmer, if ETMBIGEND changes, the ARM720T processor
changes, with the debugger unaware that the core has reset. You must also ensure
that HRESETn is held stable during debug. When the system applies reset to the
ARM720T processor (that is, HRESETn is driven LOW), the ARM720T processor
state changes with the debugger unaware that the core has reset.
ARM720T CORE CPU MANUAL
Programming breakpoints
on page 9-38.)
EPSON
9: Debugging Your System
on page
9-7
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