Epson ARM720T Core Cpu Manual page 37

Operation
Load With register offset
Address
Store With immediate offset
With register offset
SP-relative
Multiple
Push/Pop
Software
Interrupt
All thumb fetches are done as 32-bit bus transactions using the 32-bit thumb
Note:
prefetch buffer.
ARM720T CORE CPU MANUAL
Table 1-12 Thumb instruction summary (continued)
word
halfword
signed halfword
byte
signed byte
PC-relative
SP-relative
using PC
using SP
Multiple
word
halfword
byte
word
halfword
byte
Push registers onto stack
Push LR, and registers
onto stack
Pop registers from stack
Pop registers, and PC
from stack
Assembler
LDR <Rd>, [<Rb>, <Ro>]
LDRH <Rd>, [<Rb>, <Ro>]
LDRSH <Rd>, [<Rb>, <Ro>]
LDRB <Rd>, [<Rb>, <Ro>]
LDRSB <Rd>, [<Rb>, <Ro>]
LDR <Rd>, [PC, #<10bit_offset>]
LDR <Rd>, [SP, #<10bit_offset>]
ADD <Rd>, PC, #<10bit_offset>
ADD <Rd>, SP, #<10bit_offset>
LDMIA Rb!, <reglist>
STR <Rd>, [<Rb>, #<7bit_offset>]
STRH <Rd>, [<Rb>, #<6bit_offset>]
STRB <Rd>, [<Rb>, #<5bit_offset>]
STR <Rd>, [<Rb>, <Ro>]
STRH <Rd>, [<Rb>, <Ro>]
STRB <Rd>, [<Rb>, <Ro>]
STR <Rd>, [SP, #<10bit_offset>]
STMIA <Rb>!, <reglist>
PUSH <reglist>
PUSH <reglist, LR>
POP <reglist>
POP <reglist, PC>
SWI <8bit_Imm>
EPSON
1: Introduction
1-17