Table 1-1 Key To Tables - Epson ARM720T Core Cpu Manual

1: Introduction
1.3.1 Format summary
This section provides a summary of the ARM and Thumb instruction sets:
ARM instruction set
•
Thumb instruction set
•
A key to the instruction set tables is shown in Table 1-1.
The ARM7TDMI-S core on the ARM720T processor is an implementation of the ARM
architecture v4T. For a complete description of both instruction sets, see the
Architecture Reference Manual
1-6
on page 1-7
on page 1-14
.

Table 1-1 Key to tables

Entry Description
{cond} Refer to Table 1-11 on page 1-13.
<Oprnd2> Refer to Table 1-9 on page 1-12.
{field} Refer to Table 1-10 on page 1-12.
S Sets condition codes (optional).
B Byte operation (optional).
H Halfword operation (optional).
T Forces address translation. Cannot be
used with pre-indexed addresses.
<a_mode2> Refer to Table 1-3 on page 1-10.
<a_mode2P> Refer to Table 1-4 on page 1-11.
<a_mode3> Refer to Table 1-5 on page 1-11.
<a_mode4L> Refer to Table 1-6 on page 1-11.
<a_mode4S> Refer to Table 1-7 on page 1-12.
<a_mode5> Refer to Table 1-8 on page 1-12.
#<32bit_Imm> A 32-bit constant, formed by
right-rotating an 8-bit value by an even
number of bits.
<reglist> A comma-separated list of registers,
enclosed in braces ( { and } ).
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ARM720T CORE CPU MANUAL