Jtag And Test Signals; Table A-3 Jtag And Test Signal Descriptions - Epson ARM720T Core Cpu Manual

A.3

JTAG and test signals

JTAG and test signal descriptions are shown in Table A-3.
Name Type
DBGIR[3:0] Output
DBGSREG[3:0] Output
DBGSDIN Output
DBGSDOUT Input
DBGTAPSM[3:0] Output
a
DBGCAPTURE Output
a
DBGSHIFT Output
a
DBGUPDATE Output
a
DBGINTEST Output
a
DBGEXTEST Output
DBGnTDOEN Output
DBGnTRST Input
DBGTCKEN Input
DBGTDI Input
ARM720T CORE CPU MANUAL

Table A-3 JTAG and test signal descriptions

Description
TAP instruction register.
These signals reflect the current instruction loaded into the TAP
controller instruction register. The signals change on the falling edge of
HCLK when the TAP state machine is in the UPDATE-DR state. You
can use these signals to enable more scan chains to be added using the
ARM720T processor TAP controller.
Scan chain register.
These signals reflect the ID number of the scan chain currently selected
by the TAP controller. These signals change on the falling edge of
XTCK when the TAP state machine is in the UPDATE-DR state.
Boundary scan serial data in.
This signal is the serial data to be applied to an external scan chain.
Boundary scan serial data out.
This signal is the serial data from an external scan chain. It enables a
single DBGTDO port to be used. If an external scan chain is not
connected, this input must be tied LOW.
Tap controller status.
These signals represent the current state of the TAP controller machine.
These signals change on the rising edge of XTCK and can be used to allow
more scan chains to be added using the ARM720T processor TAP
controller.
CAPTURE state signal.
When HIGH, this indicates that the TAP controller state machine is in a
CAPTURE state (see Figure 9-8 on page 9-19).
SHIFT state signal.
When HIGH, this indicates that the TAP controller state machine is in a
SHIFT state (see Figure 9-8 on page 9-19).
UPDATE state signal.
When HIGH, this indicates that the TAP controller state machine is in an
UPDATE state (see Figure 9-8 on page 9-19).
INTEST state signal.
EXTEST state signal.
Test data out enable.
Not test reset.
When LOW, this signal resets the JTAG interface.
Test clock enable.
Test data in.
JTAG test data in signal.
EPSON
A: Signal Descriptions
A-3