Table 2-4 Exception Vector Addresses - Epson ARM720T Core Cpu Manual

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After fixing the reason for the abort, the handler must execute the following irrespective of the

processor state (ARM or Thumb):

SUBS PC, r14_abt, #4

SUBS PC, r14_abt, #8

This restores both the PC and the CPSR, and retries the aborted instruction.

There are restrictions on the use of the external abort signal. See

Note:

on page 7-21.

2.8.7

Software interrupt

The SWI instruction is used for entering Supervisor mode, usually to request a particular

supervisor function. A SWI handler must return by executing the following irrespective of the

state (ARM or Thumb):

MOV PC, r14_svc

This restores the PC and CPSR, and returns to the instruction following the SWI.

2.8.8

Undefined instruction

When the ARM720T processor encounters an instruction that it cannot handle, it takes the

Undefined Instruction trap. This mechanism can be used to extend either the Thumb or ARM

instruction set by software emulation.

After emulating the failed instruction, the trap handler must execute the following

irrespective of the state (ARM or Thumb):

MOVS PC, r14_und

This restores the CPSR and returns to the instruction following the Undefined Instruction.

2.8.9

Exception vectors

The ARM720T processor can have exception vectors mapped to either low or high addresses,

controlled by the V bit in the Control Register of the system control coprocessor (See

on page 3-4). Table 2-4 shows the exception vector addresses.

High address

0xFFFF0000

0xFFFF0004

0xFFFF0008

0xFFFF000C

0xFFFF0010

0xFFFF0014

0xFFFF0018

0xFFFF001C

The low addresses are the defaults.

Note:

ARM720T CORE CPU MANUAL

for a Prefetch Abort

for a Data Abort