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The CP15 register c15 operations that operate on the CAM, RAM1, and RAM2 are shown in
Table 11-5.
Table 11-5 CAM, RAM1, and RAM2 register c15 operations
Function
CAM read to C15.M
CAM write
RAM1 read to C15.M
RAM1 write
RAM2 read to C15.M
RAM2 write
CAM match RAM1 read to C15.M
For the CAM match, RAM1 read operation a TLB miss will not cause a page walk.
Note:
These register c15 operations are all issued as MCR, which means that the read and match
operations have to be latched into register CP15.M in CP15. This is a 32-bit register that is
read with the following CP15 MRC instruction:
Read from register CP15.M
Table 11-6 summarizes register c2, c3, c5, c6, c8, c10, and c15 operations.
Table 11-6 Register c2, c3, c5, c6, c8, c10, and c15 operations
Function
Read Translation Table Base Register
Write Translation Table Base Register
Read domain [15:0] access control
Write domain [15:0] access control
Read FSR
Write FSR
Read FAR
Write FAR
Invalidate TLB
Invalidate TLB single entry (using MVA)
Read TLB lockdown
Write TLB lockdown
CAM read to C15.M
CAM write
RAM1 read to C15.M
ARM720T CORE CPU MANUAL
Rd
Data
SBZ
Tag, Size, V, P
Tag, Size, V, P
SBZ
Protection
Protection
SBZ
PA Tag, Size
PA Tag, Size
PA Tag, Size
MVA
Fault, Miss, Protection
Rd
Instruction(s)
TTB
MRC p15, 0, <Rd>, c2, c0, 0
TTB
MCR p15, 0, <Rd>, c2, c0, 0
DAC
MRC p15, 0, <Rd>, c3, c0, 0
DAC
MCR p15, 0, <Rd>, c3, c0, 0
FSR
MRC p15, 0, <Rd>, c5, c0, 0
FSR
MCR p15, 0, <Rd>, c5, c0, 0
FAR
MRC p15, 0, <Rd>, c6, c0, 0
FAR
MCR p15, 0, <Rd>, c6, c0, 0
SBZ
MCR p15, 0, <Rd>, c8, c5, 0
MCR p15, 0, <Rd>, c8, c6, 0
MCR p15, 0, <Rd>, c8, c7, 0
MVA format
MCR p15, 0, <Rd>, c8, c5, 1
MCR p15, 0, <Rd>, c8, c6, 1
MCR p15, 0, <Rd>, c8, c7, 1
TLB lockdown
MRC p15, 0, <Rd>, c10, c0, 0
TLB lockdown
MCR p15, 0, <Rd>, c10, c0, 0
SBZ
MCR p15, 4, <Rd>, c15, c7, 4
Tag, Size, V, P
MCR p15, 4, <Rd>, c15, c7, 0
SBZ
MCR p15, 4, <Rd>, c15, c11, 4
EPSON
11: Test Support
11-9
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