Table 1-7 Addressing Mode 4 (Store); Table 1-9 Operand 2; Table 1-10 Fields - Epson ARM720T Core Cpu Manual

1: Introduction
Addressing mode 4 (store), <a_mode4S>, is shown in Table 1-7.
Addressing mode 5 (coprocessor data transfer), <a_mode5>, is shown in Table 1-8.
Operand 2, <Oprnd2>, is shown in Table 1-9.
Fields, {field}, are shown in Table 1-10.
1-12

Table 1-7 Addressing mode 4 (store)

Addressing mode
IA Increment after
IB Increment before
DA Decrement after
DB Decrement before
Table 1-8 Addressing mode 5
Operation
Immediate offset
Pre-indexed
Post-indexed

Table 1-9 Operand 2

Operation
Immediate value
Logical shift left
Logical shift right
Arithmetic shift right
Rotate right
Register
Logical shift left
Logical shift right
Arithmetic shift right
Rotate right
Rotate right extended

Table 1-10 Fields

Suffix Sets
_c Control field mask bit (bit 3)
_f Flags field mask bit (bit 0)
_s Status field mask bit (bit 1)
_x Extension field mask bit (bit 2)
Stack type
EA Empty ascending
FA Full ascending
ED Empty descending
FD Full descending
Assembler
[<Rn>, #+/-<8bit_Offset*4>]
[<Rn>, #+/-<8bit_Offset*4>]!
[<Rn>], #+/-<8bit_Offset*4>
Assembler
#<32bit_Imm>
<Rm> LSL #<5bit_Imm>
<Rm> LSR #<5bit_Imm>
<Rm> ASR #<5bit_Imm>
<Rm> ROR #<5bit_Imm>
<Rm>
<Rm> LSL <Rs>
<Rm> LSR <Rs>
<Rm> ASR <Rs>
<Rm> ROR <Rs>
<Rm> RRX
EPSON ARM720T CORE CPU MANUAL