Table 9-3 Instruction Encodings For Scan Chain 15 - Epson ARM720T Core Cpu Manual

9: Debugging Your System
Scan chain 15
Scan chain 15 is dedicated to the system control coprocessor registers (the CP15 registers).
There are 37 bits in scan chain 15. From DBGTDI to DBGTDO, the order of the bits is:
• read/write bit
• instruction encoding bits [3:0] (see Table 9-3)
• data bus bits 31 through 0.
Bit 0 of the data field is the first bit to be scanned in and the first to be scanned out.
The 4-bit instruction encodings for scan chain 15 are shown in Table 9-3.
Encoding
b0000
b0001
b0010
b0011
b0100
b0101
b0110
b0111
b1000
b1001
b1010
The instructions shown in Table 9-3 are only executed during update. To perform a
Note:
read, the processor must return to capture state and then shift the result out. In
the capture stage, the instruction field of scan chain 15 is RAZ.
9.11.2 Controlling the JTAG interface
The JTAG interface is driven by the currently-loaded instruction in the instruction register
Instruction register
(described in
Test Access Port
(TAP) controller.
For more information about the TAP controller, see
9-18

Table 9-3 Instruction encodings for scan chain 15

Instruction
ID register access (read only)
Control register access (read/write)
Translation Table Base Register access (read/write)
DAC register access (read/write)
FSR register access (read/write)
FAR register access (read/write)
FCSE PID register access (read/write)
TRACE PROCID register access (read/write)
Invalidate cache (write only)
Invalidate TLB (write only)
Invalidate TLB single entry (write only)
on page 9-23). The loading of instructions is controlled by the
The TAP controller
EPSON
on page 9-19.
ARM720T CORE CPU MANUAL