Epson ARM720T Core Cpu Manual page 17

Timing diagram conventions
This manual contains one or more timing diagrams. The following key explains the
components used in these diagrams. Any variations are clearly labeled when they occur.
Therefore, no additional meaning must be attached unless specifically stated.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within
the shaded area at that time. The actual level is unimportant and does not affect normal
operation.
Further reading
This section lists publications by ARM Limited, and by third parties.
ARM periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and ARM Frequently Asked Questions.
ARM publications
This document contains information that is specific to the ARM720T processor. Refer to the
following documents for other relevant information:
ARM Architecture Reference Manual
•
AMBA Specification (Rev 2.0)
•
ETM7 (Rev 1) Technical Reference Manual
•
ARM7TDMI-S (Rev 4) Technical Reference Manual
•
Other publications
This section lists relevant documents published by third parties.
Standard Test Access Port and Boundary Scan Architecture
•
1149.1.1990).
Figure 9-8 on page 9-19 is printed with permission IEEE Std. 1149.1-1990, IEEE Standard
Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE
disclaims any responsibility or liability resulting from the placement and use in the described
manner.
ARM720T CORE CPU MANUAL
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Key to timing diagram conventions
(ARM DDI 0100)
(ARM IHI 0011)
EPSON
(ARM DDI 0158)
(ARM DDI 0234).
(IEEE Std.
Preface
xiii