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ABBREVIATIONS
Adr
Address
MC
Maintenance Console
ALCH
Adder Latches to Channel
Mpx
Multiplexor
ALD
Automated Logic Diagram
MS
Main Storage
Blk
Block
Op
Operation
BT
Binary Tgr
p
Parity
cc
Command Chain
PB
Pushbutton
CFC
Control Field Chart
PCI
Program Controlled Interrupt
Ch
Channel
P/F
Pass/Fail
CHAL
Channel to Adder 'Latches
PL
Program Load
Chk
Check
Pri
Priority
CLF
Condensed Logic Flowchart
PSS
Progressive Scan Stat
Clk
Clock
PSW
Program Status Word
Cnt
Count
Com
Common
Rd
Read
Ctr
Counter
Reg
Register
Ctrl
Control
Req
Request
Cyl
Cylinder
ROAR
Read Only storage Address Register
ROS
Read Only storage
DTC
Data Transfer and Control
ROS DR
Read Only storage Data Register
Rst
Reset
ECAD
Error Check Analysis Diagram
Rtne
Routine
R/W
Read/Write.
FLT
Fault Lor.ating Test
s
Stat
G/F
Good/Fail
SAR
Storage Address Register
GP
General Purpose (Stats 0-7)
SCR
Sil icon-Controlled Rectifier
Gr
Group
SDR
Storage Data Register
Gt
Gate
Seg
Segment
Sel
Selector
HA
Hardware Address
Seq
Sequence
Hdw
Hardware
SESS
Supervisory Enable storage Stat
SIU
Suppress Incorrect Length Indication
IAR
Instruction Address Register
SIM
Simulated Check
IF
Interface Register
SP
Storage Protect
nc
Inhibit lAR Count
SS
Supervisory Stat
ILi
Incorrect Length Indication
Sto
Storage
lnh
Inhibit
Sw
Switch
lnsn
Instruction
1/0
Input/Output
TD
Time Delay
IPL
Initial Program Load
Term
Termination
lrpt
Interrupt
Tgr
Trigger
TIM
Timing Chart
LCS
Large Capacity Storage
UA
Unit Address
LCW
Linkage Control Word
ucw
Unit Control Word
Loe
Location
LS
Local Storage
Wr
Write
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