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l
POSITION REGISTER
j
CYCLE COUNTER
l
s_L;JlK
J
l
J
4
l
UA
l
CCWl
l
ccw21
UNIT
l
RD
l
WR rND
I
I
l
PHASE A STEP
J
AO
I
Al
l
STEP
l
REL~ :e~
FETCH
TYPE
TYPE
SEL
STORE
FETCH
UP
COMP
IRPT
J_ _!!_
l
_!_
12121.
L
REOUEST REG!Slf_R
J_
COMMON CHAN DETECT
J
J
[
PRIORITY
J
l l
I I
I
L
STAT
T
I
PRI
I
PRI
I
I'NH
1
4
l
1
.l 2 .l
3
.l
0
I
2
3
4
s
_l_
0
l
I
I
2
I
3 J_ LS
I
Z-3
PCI
RTNE
Bit
Indicator
ALO
Position
Description
UA FETCH
GB181
CCWI TYPE
GB181
CCW2 TYPE
GB181
UNIT SEL
GB181
0-8
The position register indicate• the routine the channel is processing or hos dane last. The nine
RD STORE
GB181
indicators are: UA, Fetch, CCW 1 Type, CCW 2 Type, Unit Sel, Rd Store, Wr Fetch, End
WR FETCH
GB18l
Up, Comp, and lrpt.
ENO UP
GB181
COMPARE
GB181
INTERRUPT
G8181
CYCLE
g
GA131
CTR
GA131
9-12
The cycle counter indicates the number af times the A clock hos eye.led through in a particular routine.
PHASE A
GA131
STEP
GA131
ro
GA111
CLOCK
Al
GA111
13-15
Indicates the position the A clock is presently in.
STEP
GA111
LS REG
GGIOI
16
Local store r!9._uest indicates when local store data is r!9._uested.
~
REQ
~81
17
_!!ogram controlled
interr~
r!9._uest indicates
~ta mosk~e ~of
interrup_t is be!!!i_ r!9._uested.
n
juDl41
PRIORITY
GBl•U
18-20
Indicates the priority of the routine requested.
GBl51
0
GB101
1
G8101
REQUEST
2
GB101
21-26
The request register, in conjunction with the selected priority, identifies the routine being requested
REG
3
GBIOI
by the channel.
4
GB111
5
GBl 11
g
GB131
STATS
GB121
27-30
Indicates the
1/0
stats used for microprogram branching in the requGSted routine.
G8121
GB131
{"
GA030
COM
PRI 1
GA030
31-34
Indicate• that the common channel ha5 detected a routine request from the channel.
CHAN
PRI 2-3 GA030
DETECT
PCI
GA030
INH RTNE GA030
35
Indicates that the detect registers (Pri 1, 2, 3, PCI) are inhibited from being set.
FIGURE 148. SELECTOR CHANNEL ROLLER - POSITION 4
188
(3/'11)
Madel 50 FEMM
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