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whether it is in the addressed byte or not. Depend-
ing upon when the error is detected, three different
actions occur with respect to SDR:
a.
If
the error is detected as SDR is being set
(latch check), the data is stored uncorrected.
b.
If
the error is detected as the data to be
stored is passing through the adder (half-
sum check), SDR does not set to the data and
zeros are stored instead. The bytes of SDR
78
(3/71)
Model 50 FEMM
which were to be replaced with data from
CPU will have been reset.
c.
If
the error is detected after storage selec-
tion but in the cycle prior to the cycle in
which SDR is set, the store operation is con-
verted to a fetch and the data is regenerated
without checking.
3. No checking is performed on data read from
the cores during a store operation.
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