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Storage
FLT Op
Location
SOR Dato
Reg (2-5)
Operation
SOR Byte 0
Comm11nts
038
80001000
0111
SOR (19-30) to ROAR; reset bin trigger.
10000000
Set ROAR to 800; word from
038 in SOR.
r~~-
80008000
0101
ROAR to SOR (6-17) and OR with next
10000000
Word from 03C in SOR.
word (mask) from storage .
. - - - - From ROAR (0).
02000000
00000010
Actual response in SOR.
{:
__
FDFFFFFF
1111
Step bin trigger if SOR (OR'ed result)
11111101
Next storage word (mask)
is all 1 's.
in SOR.
FFFFFFFF
11111111
OR'ed result in SOR.
044
FFFFFFFF
1111
Step bin trigger if SOR
11111111
Expected response in SOR.
Example 1
(expected response) is a
11
1 's.
054
80000000
Olll
SDR (19-30) to ROAR; reset bin trigger.
10000000
Set ROAR to 000; word from
054 in SDR.
c::_
80008000
0101
ROAR to SOR (6-17) and OR with
10000000
Word from 058 in SOR.
next word (mask) from storage,
. - F r o m ROAR (0).
00000000
00000000
Actual response in SOR.
{°SC
FDFFFFFF
1111
Step bin trigger if SOR (OR'ed
11111101
Next storage word (mask)
result) is all l's.
in SDR.
FOFFFFFF
11111101
OR'ed result in SOR.
060
FDFFFFFF
1111
Step bin trigger if SOR (expected response)
11111101
Expected response in SOR.
Example 2
is all 1 's.
FIGURE
27.
MASK AND EXPECTED RESPONSE EXAMPLES
code 01-05) before they are sent to the FLT op reg.
When this OR 'ing occurs, the entire word (data and
parity bits) is OR'ed with the SDR contents. This
OR'ed result remains in the SDR until replaced with
new information. The FLT op reg contents deter-
mine what operation is to be performed.
Consider a main store mode hardcore test which
sets ROAR(O) to a
1.
The actual response, ROAR
(0-11), is gated to SDR(6-17) and OR'ed with the
mask word (0-31) which is all 1 's except for bit
position six.
If
ROAR(O) is actually set to a l, the
OR'ed result wiH be all l's (Figure 27, Example 1).
If
the test is for a reset of ROAR(O), the actual
response will not have bit position six on
(if
success-
ful). This actual response will be OR'ed with a
mask of all 1 's except for bit position six.
If
this
OR'ed result is not all l's when tested, the binary
trigger will not be turnl;ld on. The second test, using
the expected response, will not step the binary trig-
ger as the expected response will not be all 1 's
(Figure 27, Example 2).
A successful test is achieved when the binary
trigger is off after the testing of the expected result.
Thus for a successful test, the binary trigger is
stepped twice (Example 1) or not at all (Example 2).
MS Mode ROS Bit Tests
The main store mode ROS bit tests consist of a
string of fault-detecting tests with one test for every
ROS bit. Each test consists of a sequence of words
in main storage. Test format is:
Word
2!?
Function
07
son (J 9-30) to ROAR and reset binary trigger
(JB-30 for emulators).
2
OJ,2,3,4
Selected ROSOH group to SOR and On with
next word (mask) from storage.
3
OF
Step binary trigger if SOR is all J's. Mask in
data field.
4
OF
Step binary trigger if son is all J's. Expected
response in data field.
5
OE
SOR (12-31) to IAR if binary trigger is off
(causes branch to specified address
+
4).
6
00
No-op (necessary to execute branch).
7
OB
Inhibit SAR clock (to loop on same word in
SOR). Word address, expected response, and
bit number in data field.
8
OA
Call for FLT load (last word of record).
Words 1-7 are repeated for every bit in the ROS
wor'd. Word 8 is the last word of the test record.
Maintenance
Feature•
(3/71)
47
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