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LCWllt 0
Add•r lth
!it 0
H
Rot
llt 0
A
o•
Latch Pulse
Scon Bit 1
E -cH
CE=3'
S•t IF Reg
*ROS Microorde"
SOR ond Scan Bit
•
8
9-10
II
12
16
17
RegilterPulM
IF
Reg
(B Bit
from
SOR)
Interface
Control(SDR 8)
Select ln
Operational In
NOTE 3
NOTE 3
NOTE 3
Scan (Must be one)
Channe I Addreu
{Mu,t
be
zero)
Reser
81,11 ln - 0
8us In - I
Sim Select In
(lnterfoc:e ControO
Sim PR2 Channel 3
Cotnmon Channel
Control(SDR 11)
PriQfity 2 - Channel 3
Priority 3 - Chonnel 3
"OT! 3
Pri(!)l'ity 3 - Channel 1
t•OTE 3
lMutt
be
zero)
PriOl'ity (Must
be
one)
A:eMt
PC! Request - Chonne I 1
LS Request - Channel 1
••1f SOR bits 9 and 10 are zero,
c;ommon channel control will be:
18
19
BVl In - 2
6v1
In - 3
u PCt Request - Channel 2 ---Mp11. Priority 2 (NOTE 1)
LS
Request -
Chonne
!
2
20
21
22
23
P(2•-3
I)
24
25
26
27
Builn-4
8v11n-5
Bus In - 6
Bus ln - 7
Busln-P
Request In
Addreu In
StatUi In
Service In
.,.. PCt Requut ·Channel 3 - - - M p x Priority
3
LS Requut - Cho"rie I 3
.,.LS Write - - - - - - - - - M p 1 1
PCt
Request (NOTE
2)
PriOJity l - ChaMel l
PriOl'ity 2 -
Channel
1
Priority
1 - Chonne I 2
Priority 2 - ChcMel 2
Priority 3 -
Channel
2
Priority l -
Channel
3
Witl-. bit 8
or.,
bits 0-1, 16-23,
P(2~-31),
2'-27 repre.ent the 15 interface lines needed to simulate
an 110 adopter.
Bits 9-10
determine which chanr.el is to
b.
used (
Mp.11: "'
00, S.I 1 "' 01, etc.).
'Nhen
bit 8
is one, 11-.e adopter con-
nected to the oddruMtd channel
i1
logically disconnected ond connected intteod to the interface positions of the
register.
With bit 11 on, the register pmitions ore re-interrupted and u111d to Mt up common channel rou!il"le reque1t controls
and priority drcuih, os indicated in the second column under forll"IClt,
Sitt 8 and 11 mutt not
be
on at the 1ame
time.
Bits 9-10 coute o scan stat to be set in the oddreued selector channel. Thit allow1
t~cificotion
of o particular s-1-
ector channel for log-out purposes.
Bit 8 may be zero in this connection,.
Bit 12 cou1es 8-11 , wl-iich remain on once .et, to
b. reset.
Wl-.en bit 12 it on in tl-.e scon-in watd, bits 8-11 must
be
z•ro.
NOTE
1: PCI
Request- chonn•l 2
still comes
on but i• not used.
NOTE
2:
LS write still comes on
but
does nothi,,g.
NOTE 3: Bitt 9-11 p9rmit stopping of
the sel.cto1
clionn91 clock at different poinfl in a 1equ.nce, These bih ore
i•t into th• SOR oddr•n keY' and ore decod•d
ot
follows:
All not•• refer to LCW bit po1itions.
FIGURE '1. INTEUACE REGISTER AND FUNCTIONS
84
(3/71)
Model 50 FEMM
0
0
0
10
II
I
0
I
I
0
I
Stop on Clock
AO
Stop
on
Clock Step Control
Stop on Clock Al
Stop on In -Tag D•loy- .. J ond
Not
2
Stop on
In ...
Tag Delay-- 3 ond Not In Tog
Stop an In .. Tag
Deloy ...... 2 and Not 3
A
Block Mo1i1er latch Pulse
(Pre1i1ents r .. etting mo1i1er
latches wliile fetching
LCW)
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