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Roller
Figure*
Position
Content
CPUl
153
3/1
L-reglster
154
3/2
M-register ,
155
3/3
M-register
156
3/4
ff-register
157
3/5
SAR byte stats
158
3/6
ROS 56-89
159
3/7
(Special feature)
160
3/8
(Special feature)
CPU2
161
4/1
ROS 0-30
162
4/2
ROS 31-55 mover function
163
4/3
Next ROS address
164
4/4
Byte ctr F-register GP stats
165
4/5
I.SAR J-register MD Gl G2
166
4/6
Check register
167
4/7
Current ROS address
168
4/8
Previous ROS address
Selector Channel Roller Analysis
The following information will aid in interpreting
the indicators on the selector cliannel roller and
logout.
Word 3
Bits 0-5 Byte Counter: Phases A and B should have
correct parity. Phase A normally equals Phase B;
if unequal:
1. On write, 'svc in' is still active.
2. The stop lines to the tag gate generator are
active from the IF register.
3. Overrun condition was detected in CCW2, in
which case BC(B) equals ER. Chain check is active.
4. During end update, ER transferred to BC(B).
5. CDA chaining occurs before the first 'svc in'
of the new record arrives and before the arrival of
new BC information. BC(B) equals ER, BC(A)
equals 00 and 'if CDA first byte LA' is active.
6. The stop channel line is active. BC(A) is 1
less than BC(B).
The byte counter incrementing is not changed in a
read backward operation; however, its output gating
is inverted.
Bits 6-7 End Register: The end register should con-
tain the count modification information obtained in
the CCW2 routine, except in the case where it is re-
set to 00 on detection of a program-type check in a
write operation. The end register should have no
effect on the channel, unless both EORl and Ll W
latches are active.
At
the end of an operation if
there are no channel check indications, BC(A, B)
equals ER.
Bits 8-10 Last Word Register:
1.
Conditions: Read op and read ready are
active, CL step is not active.
*Located at end of this Appendix
144
(3/71)
Model SO FEMM
a. If EORl is active, the lowest active LW
latch (L3W is high, LlW is low) indicates
the additional number of buffers needed
for collection of data from the interface to
complete the block of data
b,
If
EOR2 is active, the lowest active LW
latch indicates the additional number of
read store routines needed to completely
store the block of data.
2. Conditions: Write op and finish (fin) latches
are active, A clock is not active.
a.
If
EORl is active, the lowest active LW
latch indicates the number of buffers that
contain the old record.
For EOR2 with read op or EORl with write op, if
the number of full latches (C, B, LS) exceeds the
lowest active LW latch, CDA chaining is implied,
with part of the new record block resting in the
channel buffers.
At the end of a write operation, L2W and L3W
should never be active.
For any operation, if Ll W is not active, the
record has not reached the end of count as specified
by the CCW.
Bits 11-14 End of Record:
1.
EOR Cnt Intlk: Interface controls are about
to be informed that the end of the block of data
approaches. Routine request circuits wait for a
reaction from the interface controls in a read op
only.
2. EORl: The interface clocks the LW registers.
3. EOR2: Routine request circuits clock the LW
register in read op.
4. Read Intlk La: To inform the routine controls
that the interface controls have completed their use
of the LW register.
This table shows the invalid combinations of the
end of record latches:
Bit Position
11
12
13
14
Other
Count
EOR
EOR
Read
Conditiotis
Intlk
1
2
lntlk
1
-
-
1
Not Svc In
1
-
1
-
-
1
1
-
-
-
1
-
Write
OD
-
-
-
1
Write{)j)
-
-
1
-
L3W
If EORl and 'cnt intlk' are both active when 'ave
in' is not active, a write op, is in progress and a
complete short record has just been fetched.
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