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only as a result of an interrupt on the input interface
of the supervisory controls. The three types of
supervisory control interrupts and their causes are:
1.
Error interrupt -- Parity check with PSW(l3)
on.
2. Normal interrupt -- System reset, FLT load
request, storage test switches, FL T's request CPU
mode change, or logout operation request CPU mode
change.
3. Clock interrupt -- Storage holdoff or single-
cycle operation.
Error Interrupt: An error interrupt is the result of
a parity check. The parity check causes all three
clock stop triggers to be set on, thus stopping all
gated (non free-running) clocks. The parity check
also turns on the error interrupt trigger. In paral-
lel with the interrupts, the status of various manual
switches, CPU controls, and the type of error are
used to set the CPU mode request triggers (Figure
19). At the end of the error detection cycle, the
error interrupt trigger signifies that an error has
occurred, and the CPU mode request triggers indi-
cate the action to be taken. At the beginning of the
next cycle (the first cycle that the clocks are stopped),
the CPU mode request triggers are gated to the CPU
mode triggers, thus producing a new CPU control
mode on the output interface.
Normal Interrupt: A normal interrupt is the result
of a manual control operation or a request for a
change of CPU control modes. These requests show
themselves at the input interface of the supervisory
controls where they cause all three clock stop trig-
gers and the normal interrupt trigger to be set on.
The CPU mode request triggers are also set on at
this time. As in an error interrupt, the CPU mode
triggers are gated at the start of the next cycle.
Clock Interrupt: A clock interrupt is the result of a
storage holdoff or a single-cycle operation. Clock
interrupts cause all three clock stop triggers to be
turned on.
The error or normal interrupt triggers
are not turned on and the CPU control mode triggers
are not gated as in error or normal interrupt. This
allows the clocks to be controlled without changing
the control mode of the CPU.
Pushbuttons That Force ROAR: Figure 19 shows the
CE panel pushbuttons that can force a hardware ad-
dress into ROAR. The address forced is determined
by the individuai pushbutton whose function is then
executed. Many other pushbuttons on the console
cause ROS to cycle but do not directly force an ad-
dress into ROAR.
40
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Model SO FEMM
LINKAGE CONTROL WORD
The linkage control word (LCW) contains information
used in setting certain controls and ROAR for main-
tenance operations in ROS mode.
The LCW must be
put in the storage data register (SDR) before it can
be used. This is accomplished by one of two methods;
it is assembled in SDR by the diagnose instruction,
or read into the SDR from main storage. With the
linkage control word in the SDR, the following items
can be set:
1.
SDR(0-2) to sequence counter (Seq Ctr)
2. SDR(4) to supervisory enable storage stat
(SESS)
3. SDR(5) to progressive scan stat (PSS)
4. SDR(6) to supervisory stat (SS)
5. SDR(7) to 1/0 mode stat
6. SDR(l9-30) to read only storage address
register (ROAR)
Items 1-4 (Seq Ctr, SESS, PSS, and SS) are set
by microorder E -
SCANCTL in combination with
EMIT 1000. Item 6 (ROAR) is set by the microorder
n -
ROAR, SCAN.
Item 5 (I/O mode stat) is set by the microorder
1 -IOMODE. This is all accomplished by the
execute LCW kernel in ROS
(QYllO) --
two micro-
instructions immediately following diagnose instruc-
tion, or the fetch LCW kernel.
DIAGNOSE INSTRUCTION
j0pcode(83)~
f#j
111
Bl
0=~1dJ~1
131'1516
SESS
PSS
SS
DI
19 20 - - - - . . . . . - - - - 31
1/0 Mode Stat (Sum Bit 8)
ROSAddress(Surn Bits 19-31)
The diagnose instruction provides an exit from a
normal operation (System/360 instructions) to a
maintenance operation. This is accomplished by
assembling a linkage control word (LCW) in the SDR,
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