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Rote Switci'I '"S:ng1e Cycle"
Timed Single
Cycle Mode
-~
OR
A
i..----r_;m_•_d_1_;"••-1•_C~y_c~l·---~~---------C:::::r,_.......,
5wt
I
la
•
MS
Mode
ROS A.ddren "'Stop
KT271
,~Ctr Mode
N::;:::. o t' - l:::to::' : :;' :.:.:.....::=--------- --·--------------------'-,_,_..'-'------'
N
Error lnterru;t"
.....___..
I
Nooool lntMr~
Li}~
~
All Clocks Stopped
Ermr !rpt Tgr
Stor~ge
Holdoff
-
Not C:' Y <1. w2
1
l<11t C re ie (Before l /0 Breokoutfl
A
Not Error Clock
1
----r;:;:-i__
L____r---r--i
il ·
N-~"""--ol_l~'•-•_T~g•-------~ ~~;~-,~~:~·~~C~~
9
1
2
;~;"'-"'_•_op-----l~
OR [ __
r,:;ll----'N~o~t~H~o~~~l~to~p'-----------.--1--I~l,-+--+.-<1---------------~
ID-
Not
S~Ctr
Mode
(
-
Not
MS
Mode
ROI
E"o'l;----
LJ
KT 161
fo<><
Clock{j)
Lt~I
~l
A
~From
.. Port l of 2
Cn~
Ctr! 'Sroo··
MS M:xle
Not Start
\ -
Not
SOR-
ROAR
Supervisory
Sror
Not Ignore Error T gr
.........
[~
A
Gate Error Reg
ROS Mode
Scan
Out
-
OR
Error Interrupt
KT07!
Error
.__
seqc,,.
Mode
Error
lnten:_~
Normal
lnte~
Storage Holdoff
-
Not E1ror Clock
1
A
NotT;"o
Sreokin(Routine Rc:;dl
Not Hord
S~
Not Seq Ctr Mode
Not
M~.
Mode
Final St:on Decoder
Error Clock
(i}
-
Ok
,__
OR
Not
Gatod
a;113
~~=;ng
' - - '
Tg<
Mode
for
Log
Tg<
~
1
KT081
FIT
lood~
lg<
~
tltort
A
Not~~ Ctr Mode
i&l!!l:ll>~----rt-
A
~uest
for ROS Mode
Reset Sysh!·n
Check $.,.itch "Stop"
MS
Mode
Not Start
e"T'T.O
St«-
Hcldoff
Not Error Clock
ROI
Mode
Normal
En'Ot' lnte,,;pt°
ROS
{"t=
A
Erro<
lines
~
OR
Seq Ctr Mode
FLT
p,~lood
Request for MS Mode
~rrupt
Nonna!
lnterrv:::£
~
OR
1-------------J_,----,_-l-l-+4--___.---~::.::::~.:::.::.:i::
_______
L___J
- Err_o_•_R_;•g=-T;_m_• _ _
-11
PH
Not ROSOR 47
EH
A
ROS Clock On
1
1/0
&«ok
In
(Rtn• Revd.
l
A
OR
)t~ody
\noihOTd
Olli
R_!iuest for
MS Mode
§:.;!!' i _:C"' t c_< C'..M~od~•:_ _ _
-lt--
Log Tgr On
A
~ ~tll'~,~·-------li--
SDR-T
Not Hord~
A
Not MS Mode
~O~st'Sw "Not Process"
KT!
11
A
IDR-IAR
~
RJ
Error Clock©
CPU Sel Main St~e
~
NotW2
A
OR
Storage
Holdoff
B..!5!!1ch On
SOR 7
t---
R2
A
ROS
Mode
ROS
Clock
cs.•)
sh
Lr:i
(Re,.t)
J
A
r1.'.J
KT211
Main Storage
(S•t~
~
KT21 I
Main Otc. Delayed
ROS lngate
Reg Set 1/0
1/0 !!&_In
late
Reg Set 1/0
ROS
Clock
On
~
Port I
-Inhibit ROS ClockJ
J
A
ROS
l1"19Dte Set
.__]
10
Main Osc
D•loyed
J
r
'KCoii'
ROS Outgc:rte Set
Moin Osc Delayed
A
11---'-le;_t_R..;eg:_M_S
-Inhibit MS Clock
Lot<
Reg
A
r
Late
Reg
Set
MS
KC021
Select Storage
~
W2
A
StoroQe Holdoff
·-· -
'""'""~'~
-1
Clock Stop
1
,..-,
J
s
c
1-.!Se~t--rT.:::""'l---i.JNl -lnhibitCPUClock
A .__ _ _ _ •t_R_eg=-_PU_
]
Tg<r
Mo;nQsc
J
J
Rovtine Received
KC521
ROS
Clock On
Kc02i
1/0 6reokin
J
A
OR
L_ _ _
.r---.
'---1
(Gate LS Sense Amp to Bit Driv«S}
KT215
Sta<- Reody
Error Clock
Ci:
FIG\JtE 19.
SUPERVISOltY CONTROLS (PART 2 OF 2)
38
(3/71)
Model 50 FEMM
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