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Section L - MC, SDR, IAR Indicators; Data and
Address Keys
This panel section contains indicators and switches
for system maintenance and operator intervention.
Master Check Indicator
The master check light is on when any trigger in
the error register is on (KT081).
Maintenance Control (MC) Indicators
This row of 36 indicators is used with the Fault
Locating Tests (FLT's). Figure 169 shows the ALD
page, bit position, and a description of the 36
indicators.
Storage Data Register
The 36 indicators in this row display the Storage
Data Register (SDR). Bit positions O, 9, 18, and 27
display the parity of the associated byte. Figure 170
shows the ALD location of the indicators.
Data Keys
The 32 data keylever switches specify four data bytes
to be stored in an addressed location. Correct parity
is normally generated. Incorrect parity may be gen-
erated with the reverse data parity switch.
Data keys may be used to specify a selected ROS
address for display or compare. A storage address
is set into the data keys for SAR compare. The data
keys are also used to simulate bytes of data when
testing the channels. The keys can be changed without
disrupting CPU operations.
Reverse Data Parity
This switch generates incorrect parity for dataspec-
ified in the data keys. Parity is inverted for all
bytes of the word. The test light is on when this
switch is on.
Storage Select Switch
The storage select rotary switch selects the storage
area that is to be addressed by the address keys. This
switch can be moved withOutdisruptingCPU operations.
The four switch positions are: Local Storage, Main
Storage, Protect Storage, and MPX Storage (Bump).
Instruction Address Register
This row of 27 indicators displays the Instruction
Address Register (IAR). Bit positions 9, 18, and 27
150
(3/71)
Model SO FEMM
indicate the parity of the associated byte. Figure
171 shows the ALD locations of the indicators.
Address Keys
The 24 address keylever switches address a location
in a storage area. These keys, in conjunction with
the storage select switch, permit store or display
access to any location in local storage, main storage,
protect storage, and bump storage. The keys can be
changed without disrupting CP'u operations.
The address keys are also used to simulate various
conditions when manually testing the channels. (Refer
to Panel Section F - Channel Control.)
Section M - Intervention and Maintenance Switches
This panel section contains pushbutton, rotary select,
and keylever switches that are required for operator
intervention and system maintenance. The customer
and CE usage meters and a permanent storage assign-
ment chart are also located on panel section M.
Rate Select Switch
The rate switch determines the manner in which in-
structions are to be performed. Three positions are
provided: process, instruction step, and single cycle.
When the rate switch is off the process position, the
test light is on.
Process: The system operates at normal clock speed.
Instruction Step.: One complete machine instruction
is executed for each depression of the start switch,
after which the CPU returns to the stopped state.
The stop point is identical to that achieved by the stop
switch. Any machine instruction can be executed in
this mode. Input/output instructions are completed
to the interruption point. The interval timer is not
incremented while the rate switch is set to the in-
struction step position. Moving the rate switch from
process to instruction step while the CPU is running
has no effect.
Single Cycle: The CPU advances by its minimum
clock amount for each depression of the start switch,
returning to the stopped state each time. Input/output
instructions can be single-cycled to the point where
asynchronous operation begins. The asynchronous
portion starts with the next depression of the start
switch and runs to completion.
If
the start switch is
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