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the control panel switches to set stats 4-7. Steps
two and three of the halt loop decode the stats and
branch ROS to the desired routine. Logic flow for
the operations is shown on CLF 122, Interruptions/
Exceptions, in the Diagrams Manual.
Stat Setting
Figure 176 shows the GP stats that are set by the
panel switches and the logic involved. The Hex value
of the four stat bits is used on the Interruption/
Exceptions CLF chart to denote the operation. The
switch settings on the control panel bring up the
proper Stat Cons Fen lines which are gated by Set
Sts 4-7 Per CE Cons and the halt trigger to set the
general purpose stats.
Instruction Step
The rate switch set to instruction step turns on the
manual trigger (if off) and brings up the exception
line (Figure 175).
Pressing the start switch (wait
bit must be off) develops the Stat 7 Cons Fen line
allowing stat 7 to be turned on. Decode of stats 4-7
branches ROS to instruction 151. The stop trigger
is left off to allow interrupts following instruction
execution to be honored. Storage protect key is re-
stored and a branch to I-fetch is made with the H
register (instruction address) in SAR. (Refer to
CLF Interruptions/Exceptions.)
After the single instruction has been executed
and interrupts, if any, taken, the halt loop is re-
entered. Step four of the halt loop (150) turns on the
stop trigger to prevent any subsequent interruptions.
Set IC
The set IC switch enters an address, specified by the
address switches, into the IAR. Set IC develops
Set IAR to set stat 6. Halt loop decode branches ROS
to instruction 152. The stop trigger is turned on;
the address keys are set in IAR; and ROS returns
to the halt loop.
Repeat Instruction (IAR)
The repeat instruction switch causes the instruction
at the location specified by the address keys to be
repeated. Pressing the key lever switch down allows
the setting of stats 6 and 7. Stat decode causes ROS
to branch out of the halt loop to instruction 153. The
stop trigger is turned on; storage protect key is re-
stored; the address keys are set in SAR; and ROS
branches to I-fetch. At the completion of instruction
execution, the exception branch returns ROS to the
halt loop and the same routine is repeated.
160
(3/71)
Model 50 FEMM
Address Compare (IAR)
With the address compare switch in the stop position,
. an equal compare between the address keys and the
· IAR causes the CPU to enter the stopped state after
execution of the addressed instruction.
In
the sync
position, the same comparison causes an oscillo-
scope sync pulse to be generated but processing con-
tinues.
The address compare switch set to stop or sync
sets the exception branch (Figure 175) and causes the
turn on of stat 5 (Figure 176). The exception branch
takes ROS to the halt loop after each instruction
execution. Stat decode branches ROS to instruction
209 to turn on the stop trigger and set the address
keys in the L register. The L register is compared
with IAR (R register) and the storage protect key is
restored. An unequal compare allows ROS to branch
directly to I-fetch with the next address.
An equal compare between the L and R registers
causes generation of the sync pulse by instruction
107.
If
the address compare switch is set to the
sync position, ROS branches to I-fetch with the next
instruction address.
If
the address compare switch
is set to the stop position, the sync pulse turns on the
manual trigger (Figure 175) to place CPU in the
stopped state.
Note: The address compare switch in the stop or
sync position adds a minimum of 3 microseconds
(time required to check IAR keys and IC for com-
parison) to each instruction.
Display and Store
Figure 176 shows the stats that are set for each
unique display or store operation. Use the Hex value
of the stat bits to follow the CLF Interruptions/
Exceptions diagram.
All display or store operations cause stat 4 to be
set on. Store operations will also set stat 7 on. The
setting of stats 5 and 6 is dependent on the storage
area defined by the storage select switch: main,
local, protect, or bump (MPX).
Halt loop decode of stats 4-7 causes all display
and store operations to branch to logic QT220 (20A
for main storage and storage protect; 20B for local
storage and MPX bump storage). The display
timing sequence is shown on Timing Chart 208,
#T2081; the store timing sequence is shown on
Timing Chart 207, #T2071.
Display: The display pushbutton switch causes the
data at the address and the storage unit specified by
the control panel switches to be displayed. The 135
ns (any pushbutton) singleshot generates the MC
Pulse Gated line which AND's with the display PB
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