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of the blocks that are set by the scan-in circuitry
and which are sensitive, no "fed by" information
can bt') given and the word "entry" is printed in this
space.
To make
it
easy to identify these points in
th8 main list, they are referenced differently. They
are labeled Al-A9, BO-B9, etc. In the cases where
a block is fed by several nets having sequential
references, whether entries or in the main part of
the list, the references are given as AD-AG, instead
of AD, AE, AF, AG.
The only other information on Scopex concerns
those cases where a net internal to a card is sensi-
tive but does not propagate its sensitivity to a pin.
In these cases, separate lines give the index num-
ber followed by the word "card" and then a list of
the cards that are suspect.
PROGHESSIVE SCAN
Progressive scan is a method of testing the common
channel, the multiplexor channel, and the selector
channel, using no additional hardware to scan directly
into each loggable storage element. Storage elements
are set by controlling the action of the channel clocks
and by applying patterns via the diagnose instruction.
Two tapes or disks are created in FLT format,
one for testing the common channel and the selector
channel, and the other for testrng the common chan-
nel and the multiplexor channel.
The tests are written in a functional manner using
the diagnose instruction as a vehicle for controlling
clocks and the action of the I/O interface.
Each group
of tests making up a complete function is termed a
series, and each series may be divided into routines.
Each test begins from a reset condition. A pat-
tern is applied by diagnosing to ROS in a functional
manner or after having set the interface (IF) register.
Figure 41 shows details of the IF register. Each suc-
ceeding test includes ali the preceding testing plus the
testing required for the next stopping point prior to
logout.
Figures 42 and 43 show multiplexor channel
and selector channel progressive scan run and repair
procedures, respectively.
Note: Disable ROS retry by jumpering 01C-
E3C4Dll to a DOS pin before running or biasing
FLT's, diagnostics, or progressive scan.
(It
is
normal for the master check indicator to be on dur-
ing the running of progressive scan tests.)
Test Descriptions
Progressive scan tests are identitied by a series
number and a test number along with the name of
the test. A typical selector channel series is com-
posed of many individual tests. Each test performs
all the operations of the p;i;evious test plus additional
operations. An example of this appears in Figures
44 and 45.
Figure 46 shows how to determine the
length of a progressive scan test when using the re-
peat instruction with the diagnose address.
Selector Channel Clock -- 100-001-00G
The selector channel clock is stepped to each point
in its instruction scan sequence, logged out, and
compared to a known good pattern. If there is a
mismatch between logout and good pattern, the
pertinent information is printed on the printer.
Start I/O Write -- 110-101
These tests are the start of true progressive scan.
All other tests are modeled after this series.
There are 12 stopping points between issuing a
start
1/0
up to and including the second DTC of a
start
1/0
ROS routine.
The selector channel and common channel are
logged out when the start
1/0
microinstruction is
given, at break-in for the first selector channel
routine, and for each clock of each of two DTC 's
issued in start
1/0
routine.
The diagnose instruction is also used to function-
ally test the start
1/0
instruction. A description of
some of this test follows.
Figure 47 shows timing.
SIO Clock Al -- 110-101: Common and selector
channel are first reset.
Diagnose instruction is
used to scan into L register (unit address and chan-
nel), R register (command address), and M register
(command code and data address).
Next the IF reg-
ister is set with the scan bit (stops the common
channel clock) and the selector channel clock is
allowed to advance to Al. The common channel
clock will not run unless the diagnose instruction
is counting ROS cycles. The diagnose instruction
is now used with a count field of two to turn on the
start
1/0
trigger in the common channel (ROS Addr
9BE). At this point the selector channel has acknow-
ledged the start
1/0,
but
it
will not request a break-
in until its clock reaches clock step. A log is initi-
ated with the selector channel clock at Al and with
the common channel start I/O trigger on.
Reg SIO Routine -- 110-102: The common and
selector channels are again reset. The L, R, and
M registers are scanned. The IF register is set to
control the common channel clock and to set the
selector channel clock at Al. ROS Addr 9BE is
again addressed by diagnose instruction to turn on
start I/O in the common channel. At this point,
test 02 is at the same place as the end point of test
01. To advance to the next logout point, the IF
register is set to advance the selector channel
clock to clock step. A logout is taken. Normally
at this point the selector channel requests the start
Maintenance Features
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63
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