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likely be in one of the following loops:
Block 988 - No channel response
Block 98C - Start 1/0 not accepted by channel
Block 990 - Channel status bad
Block 919 - Unit status bad
Start, Step
The start and stop switches on panel section M allow
the operator to intervene in programmed system op-
eration.
The start switch initiates system operation under
control of the rate switch. After a system reset,
the start switch begins program execution with the
instruction designated by IAR. After a normal stop,
the start switch causes processing to continue as if
no stop had occurred.
The stop switch places the CPU in the stopped
state. The manual trigger is turned on and the re-
sultant exception branch causes ROS to enter the
halt loop. Store, display, and other exception-type
manual operations are dependent on the halt loop.
Figure 175 in this manual is a diagram of start,
stop, and exception logic. For start and stop sequence
timing refer to Timing Chart 210--Start, Stop, Check
Reset, #T2101. Exception logic flow is shown on
CLF 121, Basic Interruption Flow and CLF 122,
Interruptions/Exceptions, in the Diagrams Manual.
Start
Pressing the start switch after a normal stop turns off
the manual trigger to allow ROS to break out of the
halt loop and branch to I-fetch. The start switch fires
the 135 ns singleshot (any pushbutton) to bring up the
MC Pulse Ungated line. This line develops MC Pulse
Gated which AND's with the start PB switch to bring
up Start Sw. With the rate switch set to process,
Start Sw turns off both manual triggers and the stop
trigger. Manual trigger off drops the Exception line
allowing ROS to exit from the halt loop.
On
QT200, Exception
=
0 causes a branch out of
the halt loop. PSW 0-15 is set in the L Register to
restore the storage protect key; IAR is set in the H
Register and through the adder to set SAR; and a
branch is made to I-fetch. The Start PB line that is
brought up along with Start Sw develops the Pulsed
Start PB line (circled 5 on Figure 175). Pulsed
Start PB drops Hard Stop and develops the clock
controls on logic KT211 and KT221.
Stop
Pressing the stop switch turns on the manual trigger
to place the CPU in the stopped state and ROS in the
halt loop. The stop PB switch generates the same
MC pulse as the start switch. MC Pulse Gated AND's
with the stop PB switch to bring up Stop Sw which
turns on manual triggers A and B. Manual trigger A
sets Exception
=
1 to cause ROS to branch to the halt
loop after the current instruction has been executed.
Manual trigger A also turns on the manual indic.ator
and brings up Halt Trigger (KS141) to enable the
setti.ng of stats 4-7 for subsequent manual operations.
Manual trigger B on inhibits the Timer Update Signal
(Timer Tick).
The halt loop on QT200 consists of four micro-
program instructions. The first instruction samples
the control panel switches to set stats 4-7, turns off
the stop trigger, and checks for external or channel
interruptions. The second and third instructions
decode stats 4-7 for manual operation requests. The
fourth instruction indicates no manual requests have
been made and therefore turns on the stop trigger
and tests for exception. With exception held on by
the manual trigger on, ROS will continue cycling in
the halt loop waiting for operator intervention.
Halt loop manual operations (display, store, set
IAR, etc.) set stats 4-7 for the correct branch from
microinstruction two or three of the halt loop. All
branch instructions, except one, will turn on the
stop trigger to inhibit any external or channel inter-
ruptions. , The one exception is the instruction step
operation which allows one instruction to be executed
and interrupts, if any, to be taken after execution.
On
return to the halt loop, the fourth instruction
turns on the stop trigger to prevent any subsequent
interruptions.
Halt Loop Operations
Halt loop operations are performed under control of
the halt loop and GP stats 4 through 7. The
Op
Panel
to S 4-7 microorder (step one of the halt loop) sets
the stats indicated by the Cons Fen lines that are
brought up by the panel switches. The halt loop
controlled operations are:
Instruction step
Set
IC
Repeat instruction (IAR)
Address compare (IAR)
Display and store main storage
Display and store protection key
Display and store local storage
Display and store bump storage
All of the above operations, except address com-
pare, require that the CPU be in the stopped state
(ROS in the halt loop, QT200). Address compare
will force ROS into a halt loop cycle after each in-
struction execution. Step one of the halt loop allows
Appendix B--System Contzol Panel
(3/71)
159
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