Table of Contents
Advertisement
The FLT technique involves the use of test
patterns. These (FLT) test patterns are designed
to prove that each trigger can be turned on and off
and that each transistor in the combinatorial logic
connecting triggers can be controlled by each of its
inputs.
Each diagnostic test forces the system to the
state specified by a particular test pattern. This
process, called scan-in, sets the selected triggers
to the predetermined values of the test pattern in
core storage. The system is then forced to respond
to the scan-in values by allowing its clock to operate
a specified number of cycles. This process, called
clock advance, exercises the combinatorial logic
between triggers and places the system in a new
internal state. This new internal state is called the
actual response. The actual response is then made
available for analysis through a process known as
§can-out, which stores the actual response pattern
into core storage. Next, the actual response is read
from storage into the SDR, OR'ed there with a mask
word from storage, and then the OR'ed result is
tested. Following this, a second test is made with
an expected response. The result of these two tests
indicates whether the individual circuit under test
functioned properly or not. This logical comparison,
and a branch on the result, is called FLT compare
and branch.
To run FLT' s , additional paths to the storage
data register (SDR) are used. These new (scan)
paths allow the internal status of the CPU and chan-
nels to be logged (or scanned-out) to storage. FLT
op codes initiating scan-out operations are denoted
by an asterisk(*) on Figure 10. A simplified diagram
of the scan-out logic is shown on Figure 13.
FLT LOAD
An alternate method of loading FLT's into main
storage is required because the normal IPL sequenc-
ing is under ROS control and uses CPU and common
channel hardware. To achieve an alternate method,
additional hardcore controls and a new data path
direct to main storage have been provided. Ase-
quence counter and four sequence stats execute the
load operation by controlling a selector channel
clock, the same selector channel (B register) gating
to SDR, the instruction address register (IAR), and
the storage data register (SDR).
The main purpose of this alternate (FLT) load
method is to store FLT programs in main storage
even though the common channel or ROS may not be
working correctly. Another reason is to allow either
good or bad parity to be loaded into storage. Arbi-
trary bit patterns, without regard to parity, can be
loaded in this way.
42
(3/71)
Model 50 FEMM
An FLT load can be accomplished from tapes or
disk packs on a selector channel. See Figures 25
and 26. Data enter storage via the B register of the
select'or channel, the scan-out/logout logic, and
thence over the scan bus into the SDR (Figure 13).
Checking is performed in the channel and again in
CPU before the data enter storage. Every two con-
secutive words on tape (or disk) are OR'ed together
to produce one word in storage. All 36 positions of
this word are the result of the OR 'ing mechanism;
that is, the 32 data positions are the OR'ed result of
the data positions of two words on tape (or disk), and
the four parity-bit positions are the OR'ed result of
the parity generator output for each of those two
words. This OR 'ing mechanism allows bad parity
to be loaded into storage. The FLT record in stor-
age starts at location zero. There is no check for
record length; however, the controls will hang up
if
the channel does not receive an even number of words.
To convert two words on tape or disk into a
single word in storage, the channel sends a read
store request which causes a write storage cycle
using the current IAR address. If reading an odd
word (the first of each pair) from tape or disk, the
IAR counter is incremented by four (IAR
+
4 =full-
word step), storage is selected, and the word from
the B register is stored at that address. When the
next (even) word is to be stored, the IAR counter is
not incremented, the previously stored word (first
of the pair) is read out, OR 'ed in the SDR with the
even word from the B register, and is then written
back into main storage.
An FLT load can be initiated from the system
control panel but not from a remote operator control
panel.
It
can also be initiated by the diagnose in-
struction via the execute LCW kernel and the FLT
load call kernel in ROS, or while performing a
maintenance operation, in either main store or ROS
mode, by inserting op code A in the FLT op register.
When loading FL T's from the system control
panel, the unit to be started is specified by the
channel and unit rotary switches (load unit switches)
on the system control panel. If a channel other than
a selector channel, or a device other than a tape
drive or disk is specified, the FLT load will not
perform, and the FLT controls will hang up.
Load From Tape
To initiate a FLT load from tape via the system con-
trol panel, the FLT mode switch is placed in the
load position, the system reset PB is depressed,
and then the load PB is depressed. (System reset
does not occur automatically as in normal IPL and
must be performed manually.) The FLT load from
tape resets the IAR
to zero, sets the sequence
counter mode trigger on, and simulates a start 1/0
operation with a read data -command.
Advertisement
Table of Contents
