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depressed during this time, the next cycle is taken.
If an interruption results, the interruption sequence
is not automatically executed but must be single-
cycled. Moving the rate switch from process to
single cycle while the CPU is running stops the CPU.
The stopped state for single cycle is one in which
no CPU clocks are running.
In
the normal stopped
state, ROS is running and executing the halt loop.
Start PB Switch
The start pushbutton switch starts system operation
as defined by the rate switch. If it is pressed after
a normal stop, it causes continuation of instruction
processing as if no stop had occurred. If it is
pressed after a system reset, the instruction desig-
nated by the instruction address register is the first
one executed.
Stop PB Switch
The stop pushbutton switch causes the CPU to enter
the stopped state. The stopped state is indicated
by the manual light being on. The transition from
operating state to stopped state occurs at the end of
instruction execution. When the CPU is in the wait
state, the transition takes place immediately. All
interruptions which are pending and not masked off
are taken, causing the old PSW to be stored and the
new one fetched before entering the stopped state.
System Reset PB Switch
The system reset pushbutton switch resets the system
to its initial state. The switch is active in all modes.
The general status of the system after a system reset
is:
1. CPU is in the stopped state.
2. All pending interruptions are eliminated.
3. Each channel in the system receives a reset.
The channels, in turn, issue a general reset to the
1/0 interfaces. (Off-line control units and I/Ode-
vices are not reset.)
4. All error indicators are reset. Errors
occurring during initialization will show.
5. All local store registers are set to good
parity.
6. The bump area of main storage is set to good
parity. The DA word is set to zero. The other
three words associated with each subchannel are
set to
07000000.
7. The instruction address register is set to
zero.
8. The L, M, H, R, J, and MD registers are
set to good partiy.
9. The FLT
Op
register, pass and fail triggers,
ignore error
1/0
trigger, and progressive scan stat
are reset.
PSW Restart PB Switch
The PSW restart pushbutton switch causes a system
reset followed by a load PSW operation from storage
location zero. At completion of the load PSW, the
CPU chang0s from stopped to operating state. This
switch is active in all modes.
Check Reset PB Switch
The check reset pushbutton switch resets all check
triggers in the error register and turns off the
master check light.
Set IC PB Switch
The set IC pushbutton switch enters an address into
the instruction address register. The address is
specified by the address keys. This switch is active
only when the CPU is in the manual state.
Store PB Switch
The store pushbutton switch stores information in an
addressed location. Data specified by the data keys
is placed in the location specified by the address keys
and the storage select switch. Storage protection is
ignored. The store switch is active only while the
CPU is in the manual state.
Display PB Switch
The display pushbutton switch causes information in
an addressed location to be displayed. The switch is
active only while the CPU is in the manual state.
The information at the storage location specified
by the address keys and the storage select switch is
displayed in the following indicators:
Indicators
Main
Storage Data Register
Local
L Register (CPU Roller #1, Roller Switch
Position
#
1 )
MPX
(Bump)
Storage Data Register
Protect
F Register (CPU Roller #2, Roller Switch
Position
#4)
Log Out PB Switch
The log out pushbutton switch causes a complete log
out of CPU and channel status. This log out is iden-
tical to that which occurs when an error is detected.
Appendix B--System Control
Panel
(3/71)
151
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