Table of Contents
Advertisement
Bit 15 BAC Latch:
If
the B almost changed latch is
active:
1.
For read operations, the preceding or present
transfer is from the B register.
2. For write operations; the present storage data
transfer is to the B register and the channel has not
finished with the data transfer.
1
BAC
1
and •u; full' should never be active at the
same time.
Bit 16 LS Enable: A priority 1 request should not be
present if LS enable is active. LS enable, u; full,
and B full should not be active concurrently.
1.
For read operations, if u; enable latch is
active, the contents of the B register will be or are
being transferred to the buffer in u;, If u; full is
also active, the LS DTC is active.
2. For write operations, if the LS enable latch
is active, the buffer in LS is available for new data
from main storage.
If
u; full is ai.so active, the
data has not been transfered from u; to the B
register.
Bits 17-19 Register Full:
BAC ENA Full Full
Operation
Bit
Bit
Bit
Bit
Description
15
16
17
18
---
0
0
0
1
Data in B register.
---
0
0
1
-
Data in LS.
Read
0
1
0
0
Illegal.
"
0
1
0
1
LS routine in progress; LS DTC
has not arrived;
"
0
1
l
0
LS DTC present.
"
0
1
l
l
Illegal.
"
l
0
0
0
Previous routine: B to main
I
storage.
"
I
0
0
1
B being or just transferred to
main storage.
"
I
l
0
0
Illegal.
"
I
l
0
I
B to main storage. C full active.
one cycle to end read store
routine.
---
I
-
I
-
Illegal
Write
0
I
0
0
Last fetch transferred to B via
I..S.
"
0
1
0
l
Data in B after transfer via LS.
"
0
l
l
0
l.S routine in progress, l.S DTC
has not arrived.
"
0
l
l
I
l
Illegal.
"
1
0
0
0
Write fetch routine in progress,
data destined for B register.
"
1
0
0
1
Write fetch step 2, clock AO or
Al.
"
1
1
0
0
Jllcgal.
Bits 20-26 Read, Write Latches: Any active indica-
tions in both the read and write groups at any one
time are signs of malfunction.
Op
Rdyl
IF
21
rad
Br
22
2:l
Description
Writ<' Bits
24
25
1
2H
(I
o
T
(I
Not performing that operation.
0
( ) I
I
I
lll<•gal.
0
I
,
0
llll'gal.
0
I
I
I
I
Illegal.
l
()
I
()
Channel in CCWI or CCW2 routine not CDA
I
I
0
I
I
I
chaining.
Channel working in routines other than above.
I
I
0
i
Chamwl performing unit selection.
I
I
l
I
l
Channel waiting to perform
an~·
of the above.
Bits 27-35 Channel Checks: 'Sim check' signals the
channel to terminate the operation. Unit status will
not be available for the CSW. Three conditions set
sim check:
1.
Channel discovered a check condition before
the unit could be selected to perform the operation.
2. A halt I/O terminated the current operation.
3.
An
IF control check occured to disconnect the
unit by a selective reset.
Word 4
Bits 0-8 Position Register: Only one position in this
field should be active at any one time.
If
none of the
positions is active, the channel is in one of two
states:
1.
Idle (instruction scan latch is active).
2. Unit selection routine is finishing or has just
finished; rd rdy or wr rdy latch is active.
The CCWl type position is used for:
1.
Start I/O routine.
2. CCWl routine.
3. TIC routine.
If
the end up position is active and the PCI req is
active, the CPU may be masking interrupts for this
channel.
Bits 9-12 Cycle Counter Phase A: Only one position
in this field may be active at any one time.
If
no
bits are active, the channel has either:
1.
Completed unit selection (MP C2, C3, C4
latches are all active).
2. Completed CCW2 routine previously.
If the A-clock A and B latches are not active, the
number associated with the active light indicates the
number of clock sequences (AO, Al, CL STEP equal
one sequence) that have occurred and are associated
with the routine in the position register.
Clock step pulses advance the cycle counter
if
clock step is active; the channel gating is associated
with the cycle counter step previous to the one that
is active at the time.
Appendix B--System Control Panel
(3/71)
145
Advertisement
Table of Contents
