Table of Contents
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Figure
Title
Page
Figure
Title
Page
101
Reset Pulses (Clock Rwming)
107
APPENPIX B - SYSTEM OPERATION
102
A Clock •
107
136
System Control Panel •
141
103
Cycle Counter
108
137
Common Channel Roller - Position
1.
162
104
B Clock •
108
138 '
Common Channel Roller - Position
2.
162
105
Tag Generator
108
139
Common Channel Roller - Position
3.
163
106
Singleshot Timing Procedure
109
140
Multiplex Channel Roller - Position
4.
163
107
Selector Channel Clock-Stepping Block Diagram •
110
141
Multiplell Channel Roller - Position
5
164
108
1052
Singleshot Timing Procedure
112
142
Multiplex Channel Roller - Position
6
164
109
1052
Read Sequence •
113
143
Multiplex Channel Roller - Position
7
165
110
1410/7010
Emulator Delays
115
144
Multiplex Channel Roller - Position
8
165
111
Emulated
7070/74
Operation Code•
(4
Parts)
116
145
Selector Channel Roller - Position
1 •
165
112
Power On Sequence
120
146
Selector Channel Roller - Position
2 •
166
113
Power/DC Off Sequence •
121
147
Selector Channel Roller - Position
3 •
167
114
Converter-Inverter Testpoints and Waveforms
121
148
Selector Channel Roller - Position
4 •
168
115
Converter-Inverter (Cover Off)
122
149
Selector Channel Roller - Position
5 •
169
116
Converter-Inverter Test Points
123
15,0
Selector Channel Roller - Position
6 •
170
117
Voltage Regulator Test Points
124
151
Selector Channel Roller - Position
7 •
170
118
Overvoltage Adjustment •
125
152
Selector Channel Roller - Position
8 •
171
153
CPU
1
Roller - Position 1
171
154
CPU 1 Roller - Position
2
172
LOCATIONS
155
CPU
1
Roller - Position
3
173
119
POU CB and Switch Layout
127
156
CPU
1
Roller - Position
4
174
120
Model
50
Frame and Gate Locations
128
157
CPU
1
Roller - Position
5
175
121
Power Distribution Frames
(2
Parts)
129
158
CPU
1
Roller - Position
6
176
122
Relay and Contactor Location Chart
131
159
CPU
1
Roller - Position
7
177
123
Circuit Breaker Location Chart
132
160
CPU
1
Roller - Position
8
177
124
Fuse Location Chart
132
161
CPU
2
Roller - Position
1
178
125
Voltage Regulator Locauon Chaft
133
162
CPU 2 Roller - Position 2
178
126
Voltage Divider Assembly
134
163
CPU
2
Roller - Position 3
179
127
Overvoltage Assembly
134
164
CPU 2 Roller - Position
4
180
128
1/0 Gate Terminators
135
165
CPU
2
Roller - Position
5
181
129
1/0 Interface Connections
136
166
CPU
2
Roller - Position
6
181
130
1442
Address Card Locations and Plugging
136
167
CPU
2
Roller - Position
7
182
131
1443
Address Card Locations and Plugging
136
168
CPU
2
Roller - Position
8
182
132
2821
Address Card Locations and Plugging
137
169
Maintenance Control Indicators
183
133
TAU
(2400)
Address Cards Locations and Plugging
137
170
SOR Indicators •
184
171
!AR Indicators •
184
172
ROS Function Check
184
173
System Reset
185
APPENDIX A - SYSTEM CHARACTERISTICS
174
Initial Program Load
186
134
IBM
2050
Processing Unit
138
175
Start, Stop, Exception Logic
187
135
IBM
2050
Frame and Gate Layout .
138
176
Control Panel Stat Setting
188
vii
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