IBM System/360 2050 Maintenance Manual page 163

INSTRUCTION REPLY l't!CO
ON TIME
0
REPLY BCHI IRPT OUT
FOUL
Bit
Indicator ALO P06ition Description
START
1/0
KEOOl
TEST 1/0 KEOOl
0-3
The CPU generated
1/0
instruction turns on the appropriate indicator - Start
1/0,
Test
1/0,
Halt
1/0,
or
HALT 1/0 KEOOl
Test Chan. The indicator is on until the channel responds.
TEST CHAN KEOOl
CHAN
{
~
KE021
NUMBER
KE021 4-6 Selected channel number in binary.
KE021
fl
KE051
INSTR KE051 7-10 Indicates the condition code with which the channel responded to an
1/0
instruction.
REPLY KE061
KE061
REPLY KE071
11
Reply is on w_lten a reel_y to on in1truction is receivedjrom a channel.
BLHI KE141 12
liancn on i:liannel interrupt !Son whenewr an unmasked channel want. to interrupt. The latch os checked
by the microprogram during I - fetch
~D_QN~ lill_Q!
13 Proceed on onterr'!f_I i• turned on
_El_
a ·~~om ~on r!f!l_ to~·
TIME OUT KE091 14 Time out is on after
on
I!?
instruction or proceed on interrupt is given to the
ChanneT
andLPUhos not
~U~K
received a r!e.!r_for 74 usec.
~1
_1_5 _T'ime out
Clie~
is on !£.an answer " not received _!rem
~ ~ann!'_ ~er
tome out.
FOUL KE091 16 Foul i• on if there is
O_E~Dm
check on a start
!L' . _O
in•truction that i•
detected~
CPU
micr~ogrom.
17-35 Not used.
FIGURE 137. COMMON CHANNEL ROLLER - POSITION 1
EARLY CHAIN
SBCR
RTNE PCI BREAK 1/0 FIRST FIRST FIRST LS
LS CHAL ALCH LAST BREAK
RECD ENABL IN RINE CYCLE CYCLE CYCLE RO
WR OTC OTC CHAIN CYCLE OUT
33
Bit
Indicator ALO P06ilion
Description
RTNE RCVD KE301 0 Routine received i• on when o
r~uesl
to break into CPU ;, Jll:Onted.
PCI ENABL KE131 1 PCI enable i1 on during a PCI routine.
BREAK IN KE301 2 Break in is on after a routine received s.!s_nal hos been received and
bre~
in is
occurr~
!L2_
RTNE KE311 3
!L' . _O
routine is on whenever on
1/0
routine i• being proceHed.
EARLY FIRST CYC KE301 4
::§~first ~
i• on earll'.. in the Finl =r_cle of an
.!ZQ_
routine.
FIRST CYC KE301 5 Finl cycle i• on during_ the first C}'Cle of an
1/0
routine.
CHAIN FIRST CYC KE321
6
Chain first cycle is on during the first cycle of a chained routine. (One routine i• fini1hed and the
next started without CPU
breaki~inJ_
LS RD KE471
7
Local store read is on during o local •tore read routine when data is tranlferred from the B register lo the
local •tore buffer.
LS WR KE471 8 Local store write i• on during a local store write routine when dato is tronaferred from the local store buffer
to the B r'!i!ster.
CHAL OTC KE441 9 Channel to adder latch data transfer and control i• on When the micro-order i• given telling a •elector
channel to transfer information Fram the channel lo the adder latch.
ALCH OTC
KE441 10 Adder latch to channel data transfer and control i• on when tne micro-order i• giwn telling a •elector
~hannel
I<> transfer information from the adder latch to the channel.
CHAIN KE321
11
Chain i• on
dur~
the last c:.tcle of a routine and indicate• !!!_at
ano~
routine i• to
E
~ined
into.
LAST CYC KE321 12 Last cycle i• on during the la1t cycle of a routine and indicates that Chaining ta another routine will
not occur.
BREAK OUT KE321 13 Break out is on when a routine is completed and CPU and ROS ore restored to the paint they -re at
before break in.
{
0
KE381
SBCR 1 KE381 14-17
Storage byte control regi1ter is used by the selector channel to designate the bytes that are to be placed
2
KE381 placed in storage during a read store.
3 KE:l81
18 Not Used
{
~!
KE441
ROS
KE441
19-20 ROS bit. 33 and 34 represent timing •ignals to the channel
(1/0
mode).
BITS -47 KE321
21-22 ROS bib -47 and 48 represent control •ignals to the channel (1/0 mode).
48 KE321
FIRST CYC CHK KE531 23
First cycle check is mode during the first cycle to make sure that ROS is really in the first cycle of an
1/0
routine.
24-35 Not used.
FIGURE 138. COMMON CHANNEL ROLLER - POSITION 2
162 (3/71) Model 50 FEMM