IBM System/360 2050 Maintenance Manual page 53

ROS Kemel Test
Using Word Bit>
Function
1 0, 1
PSW 32,33
3,4 M byte ctr
5 - 8 Length ctr
#
2 (G2)
12-15 J
Reg
16-19 MD ctr
21 -24 F Reg
26-31 PSW 34-39
PO P3
Byte Stal>
2
o,
1
Sets carry stat if either bi.I is on
8- 11
Storage protect key (PS W 8 - 11)
15-16 Syllable in op buffer stat is set to one
if bath bit> equal zero
23-30 PSW 0- 7
PO-P3
General purpose stats 4 - 7
3 0 L sign stat
Sean - In
24-27 Length ctr # 1 (G 1)
31
Q
Reg
Pl - P3 CPU mover function reg
4 0 R sign stat
12-15 PSW12-15
PO-P3 General purpose stats 0- 3
5
30-31 L byte ctr
P2-P3 Local stare function reg
6 30-31
1/0
reg
P3,P2,Pl I/
0
mover function reg
7 M reg
B L reg
9 R reg
10 I/
0
interface reg
11
H reg
FIGURE 31. FLT CYCLE TESTS: WORD FORMAT
Scan-In
The first 11 test words are used to place known
values in various registers via the scan-in kernel.
This kernel takes 11 consecutive words, addressed
by the IAR, to perform the operation. It does
nothing else to IAR except advance the address prior
to reading the next word from storage.
Fetch/Execute LCW
At the completion of the scan-in sequence, test word
12 is read from storage into the SDR via the fetch
LCW kernel. Word 12 is a linkage control word
(LCW) whose contents are set into ROAR, the se-
quence counter, the supervisory stat (set on), the
progressive scan and supervisory enable storage
stats (set off), and the 1/0 mode stat (set according
to SDR (7) of the 12th word). The LCW contents are
set into the preceding items via the execute LCW
kernel.
Clock Advance
At this point ROS executes the ROS word specified
by ROAR, and the sequence counter is stepped up
by one. This operation is repeated until the sequence
52 (3/71) Model 50 FF.MM
ROS Kernel Test
Using Word Bits Function
12 0-2
Sequence counter
Fetch/
4
Supervisory enable storage stat
Execute LCW
5 Progressive scan stat
6
Supervisory stat
7 I/
0
mode stat
19-30 ROAR (18- 30 far emu lato11)
Scan- Out
13 Actual response address
14 Mask address
15
Mask
16
Expected response {word to be tested)
17 (X)
Starting address this test
(used 15 times)
18 (X+l) Starting address next test
(goad test or start after
cheeking failure)
19 (X+2) Tennination bit (7)
and Seopex
FLT Compare
infonnation
and Branch 20 (X+3) Starting address this test
(restart after tenn ination)
21
(X+4) Starting address next test
(forced pass after tennination)
22 Test number and segment number
counter equals seven, which occurs after one or two
cycles for the tests being described. When the se-
quence counter steps to seven, a hardware address
(2CO) is forced into ROAR. This address is the be-
ginning of the scan-out kernel.
Zero-Cycle: If the ROS word used during clock
advance is 000, we have a zero-cycle test. When
a trigger is being tested, three patterns are applied;
the first and third reset the trigger, and the second
sets it. A random pattern is applied to all other
triggers while any particular trigger is being tested
to help in the detection of noise and interference
problems.
One-Cycle: The ROS word used in one-cycle tests
allows a data transfer within CPU. This is normally
accomplished in a single cycle except for two areas
in which two cycles are needed (segments 4 and 6).
Scan-Out
The scan-out kernel stores test words 13 and 14 in
hex address locations 80 and 84 for future use in the
compare and branch kernel. Next, scan-out of the
various registers and stats is begun. Contents of
CPU registers and triggers (14 words) are stored