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Word 2 causes a portion of the ROS data register
(ROSDR) to be placed in SDR. Word 3 is a mask
word and is OR'ed into SDR by inhibiting the normal
SDR reset. This mask consists of l's in all positions
except for the bit position to be tested. The op por-
tion of this word causes an all l's test to be per-
formed on the SDR. If the test is met, indicating
that the bit being tested is a l, the binary trigger is
stepped.
Word 4, the expected response, is placed in SDR
and the all l's test is repeated.
If
this test is met,
indicating that the expected bit is also a 1, the binary
trigger is stepped again.
If
both the actual response
bit and expected response bit are 1 's, the trigger
will have stepped twice and will be off. Similarly, if
both bits are O's, the trigger will be off. The trig-
ger is on only
if
the actual response bit and expected
response bit differ; therefore, it serves as the basis
for a pass/fail decision.
Word 5 tests the binary trigger; if it is off, the
program branches to the next test.
If
this condi-
tional branch·is not taken, indicating that the bit
under test has not been read out correctly, word 7
is executed continuously by inhibiting the SAR clock.
The effect is that of a diagnostic stop; the data por-
tion of this word contains the address of the ROS
word under test, and the bit in error. This infor-
mation is displayed in the SDR. Figure 28 is a
typical example of a ROS bit test.
Testing may be continued after a diagnostic stop
by pressing the start pushbutton. When a fault
exists, it normally causes many tests to fail. For
example, a faulty sense amplifier indicates the same
bit is incorrect in many unconnected words. By
examining the addresses (both word and bit position)
of every diagnostic stop, some measure of fault-
localization is possible.
Running time for the test tape containing the ROS
bit tests, and the hardcore tests preceding them,
is approximately 3-4 minutes (on a good machine
with no failures).
ROS MODE FLT's
ROS mode FLT's are the second step in the "boot-
strap" sequence begun with the main store mode
FLT's. They are on the FLT ROS mode tape (or
FLT disk pack 4) and are loaded with an FLT load.
ROS mode FLT's are executed under microprogram
control and assume a properly functioning ROS.
48
(3/71)
Model 50 FEMM
No
Na
Off
Op E
SOR
ta
IAR
Op 7
SOR to ROAR
Reset Bin Tgr
Op 1, 2, 3, or 4
ROS Group to SOR
OR Mask to SOR
Step Bin Tgr
Ex pee ted Response
ta SOR
Step Bin Tgr
On
FIGURE 28. MS MODE ROS BIT TEST
Op F
Op F
OpB
Stop
The ROS mode FLT's consist of hardcore tests,
zero-cycle tests, and one-cycle tests.
ROS Mode Hardcore Tests
The ROS mode hardcore tests (Figure 23) check out
the pass/fail triggers, control stats and counters,
and the scan-in and scan-out kernels in ROS. The
tests are executed via a series of linkage control
words (LCW's) which exercise specific micropro-
gram steps used by the FLT controls. Failures
cause a halt or loop, and a listing must be consulted.
These tests are placed first on the ROS mode FLT
tape. See Figure 29 for a hardcore test sample.
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