Table of Contents
Advertisement
1/0 routine and the common channel breaks in.
However, since the common channel clock is stop-
ped, t.he detect registers will not turn on even
though the selector channel has provided a priority
request.
Reg SIO Routine --
110-103:
This test is the same
as the previous test, except that the clock pulse is
allowed to run at normal machine speed
(100
ns)
rather than be at a de level at logout. After the
start I/O trigger is turned on, the IF register is
set to allow the selector channel clock to advance
from Al through clock step. A logout is taken at
this time.
Break-In SIO Routine --
110-104:
The channel is
reset and the L, R, and M registers are set
prior to diagnosing to start I/0.
The IF register
allows the selector channel clock to advance past
clock step
8.S
in test
03.
Because the selector
channel has a priority request pending, the only
requirement of the common channel is that it turn
on a detect register and break in to the CPU. Be-
cause the common channel clock is stopped, it is
necessary to get it running to break in. This is done
by diagnosing to a ROS NOP (919) for a count of
three. A count of three allows for a break-in and
execution of the first micr::>instruction of the I/0
routine. An exit can be made from the routine to
a linkage control word at this time in order to pre-
pare the IF register (selector channel clock) for any
DTC's in the I/O routine. A logout is taken at break-
in time.
First DTC AO SIO --
110-105:
The channel is exer-
cised to exactly the same place as in the previous
test at logout time. It has executed the first micro-
instruction of the start 1/0 routine. An exit is now
made from the I/O routine, and the IF register is
set to stop the selector channel clock on AO.
Next
the linkage control word goes to the next ROS ad-
dress in the routine for a count of two in order to
issue the DTC to the channel. When the DTC is
issued, the selector channel clock steps to AO. A
logout is taken here.
First DTC Al SIO --
110-106:
Everything is the
same as the previous test except when an exit is
made from the I/O routine after break-in, the IF
register is set to stop the selector channel clock
on A 1. The diagnose instruction calls on the second
microinstruction of the SIO routine for a count of
two, and the selector channel stops on A 1. A logout
is taken.
Remaining tests are applied in the same fashion.
The selector channel is forced to a known state (not
necessarily a reset state). Then the common chan-
nel is run to break in and issue DTC's. However, it
is necessary to set the IF register in order to con-
trol the selector channel clock.
Test Patterns
The method used to obtain the good patterns is to
apply the tests, logout the common and selector
channels, and record the logout data as "good ma-
chine" patterns. Tests identical to those used for
pattern generation are run, and the logout is com-
pared to the pattern residing in storage.
If
a mis-
match is sensed, the same type of information as
provided in the selector channel clock test is given.
Selector Channel Tape or Disk
The tests on tape and disk appear in the following
sequence:
1.
Hardcore -- These tests check the hardware
needed for running the progressive scan tests.
2. Common Channel -- These tests check the
common channel for channel O operations (or chan-
nels
1, 2,
or
3,
depending on the system configura-
tion).
3. Selector Channel -- These tests exercise the
external selector channel.
The tests are arranged so that the greatest
coverage occurs in the first few series.
The first two records contain the progressive
scan selector channel control program which is used
to compare the logout of the machine to a known
good logout. The print section of this control pro-
gram prints or types a heading and a list of the fail-
ing triggers. The heading contains the test number
and name, the time of failure (log point), the sync
point, the loop numoer (used for detecting intermit-
tents) and the diagnose address (for looping).
Selector Channel Clock Control
Progressive scan tests the common channel and
selector channel together. Both the common and
the selector channel clocks are controlled by the
diagnose instruction. Tests can therefore be run
so that selector channel A clock can be stopped on
any clock pulse for each data transfer control (DTC)
signal issued by the common channel.
Either a DTC signal or a pulse from the IF reg-
ister will start the A clock, causing the clock to
advance through one cycle. DTC must fall to allow
the clock step control signal to rise (Figure 48).
Clock outputs then initiate a series of predetermined
channel actions. The particular routine performed
determines the numbe_r of DTC signals sent to the
selector channel.
Maintenance Features
(3/71)
71
Advertisement
Table of Contents
