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Po• 4
Poe 5
Po• 5
Po• 6
Bit 9
Bits4-5
Bit 0
Bit 16
----
----- ----- ----
Remark•
Cycle
Position
Counter A-clock
Register Finish
Step 0
C,D latch Transfer Latch
1
0
1
1
Request register equals
position register; first clock
sequence in routine has not
occurred.
-
0
0
1
Last clock sequence in
routine has occurred (unit
select and CCW2 are ex-
ceptions). New request
register can transfer to
position register.
-
-
0
0
The routine in the position
register ts being proceHed
and
ts not associated with
the routine in the request
register.
-
0
1
0
Illegal.
Bits 13-15 Clock AO, Al, Clock Step: Only one light
should be active at any one time.
If
one position is
active the clock is:
1. Stopped by the setting of the interface register.
2. Stopped because of an error detection outside
of the clock circuitry.
3. Stopped because of a clock malfunction.
For analysis of the A clock see word 5 bits 2-5.
Bit 16 LS request: Channel wishes to perform LS-B
transfer. No LS request should exist if:
1.
On read, LS full is active.
2. On write, LS full is not active
If
LS enable is also active, the LS routine is be-
ing serviced, but the LS DTC is still to come.
Bit 17 PCI Request: Channel wishes to present
status information to CPU.
1. If
'PCI req,' 'end up (position register), and
'rec end' are all active, the channel has stopped
record transmission to the unit. C register bits
8-15 contain the unit status.
2.
If
'PCI req' and 'poll' latches are both active,
the unit presented status while the channel was idle.
C register 0-7 contains unit address; C register 8-
15 contains unit status.
3. If 'PCI req' is active with either 'IF read' or
'IF write' active and 'rec end' is not active, the
request is due to the PCI flag.
Bits lS.-30 Request Register: Positions 21-26 should
have only one position active at any time, except for
unit select routine where bits 2 and 4 are active.
There should be at least one active priority bit if one
position in 21-26 is active.
146
(3/71)
Model SO FEMM
If
the 'fin' latch is active when the request regist-
er contains a request, the request should be in the
position register and the common channel has not
yet sent a DTC associated with the routine (the 'inh
rtne' indication should not be active).
If
the 'fin'
latch is not on, the channel has not transfered the
request into the position register.
Bits 31-35 Common Channel Detect:
1.
PCI:
If
PCl's is active, the CPU has issued a
proceed with interrupt signal, the interrupt mask is
not active and the common channel is in the break-
in cycle.
2. Inh Rtne:
If
the inhibit routine is active, the
selector channel has not responded to the first DTC
associated with the routine serviced by CPU.
Further requests from the channel will not be con-
sidered in the priority matrix until the channel
passes through step 0 clock Al time.
IB
Request
IB
Detect
(pos 16)
(pos 31)
---------
---------
Remarks
Priority 1,
Pr! 1 detect (32)
2 or 3 request
Pri 2-3 detect (33)
in Se) Ch (18-20)
1
0
Either
IB
detect inhibit
latch (for a local store
request) (not indicated)
inhibit routine latch (for a
priority 1,2, or 3 request)
(pos 35), or the routine
received latch is active.
0
1
The routine received latch
is active and the channel is
selected for a routine
break-in cycle.
1
1
The channel has responded
to a previous routine
and
the request is not being
serviced.
Word 5
Bit 0 Position Register Transfer:
If
bit 0 is active
together with cycle counter step 0 and the 'fin' latch;
the request register equals the position register and
the first clock sequence in the routine has not
occurred.
Bit 1 Inh Rd Store: If bit 1 is active, the last word of
data has been stored in CPU even though some of the
register full indications are active. Too many bytes
were accepted by the channel before the record
count information was available in the CCW2 routine
when CDA chaining.
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