IBM System/360 2050 Maintenance Manual page 150

General
P~e
Latches
Channel State
1
f
2
3 4 5
6
7
0 0 0
0 0 0 0 Idle to CCWI, Step 1
BC lnfo 0
0 Rd
Back- WR CCWl, Step 1 to
Cp wards
Op
CCW2,St~l
BC Info 0
0 0 0 0
CCW2, Step 1 to
CCW2,Step 2
BC lnfo
LR Info
LIW L2W L3W CCW2, Step 2 to
CCW2,Step 3, Al
BC lnfo
0 0 LlW L2W L3W CCW2,Step 3A, to Rd
Store or Wr Fetch
MB CR Info
LlW L2W L3W Rd Store
BC Info 0 0 LlW L2W L3W Wr Fetch
Original
-l
-
BC Final LlW L2W L3W End up (Rd) to
or Intrpt to Reset
Comp
BC lnfo
0 0
LlW L2W L3W End up (WR) to
Original or lntrpt to Reset
Comp
Bits 11-15 Flag Register: This regiater stores the
special conditions that the channel command word
(CCW) designates for the operation. Flag register
positions correspond to flag bits in the CCW. The
positions are: chain data, chain command, suppress
incorrect length indication (SILi), skip, and program
controlled interruption (PCI). The set state of any
flag register position causes the channel to deviate
from normal procedures in executing the operation.
Except in write chain data operations, the channel
sets the flag register while processing the second
half of the channel command word (CCW2):
An active CDA flag resets the CC and SILI flags.
The CC flag is reset also when control word chaining
is suppressed because of checks detected by the in-
terface controls.
Bit 16 Fin Latch: The last clock sequence in the
routine has occurred; new request register infor-
mation can transfer to the position register.
Bits 17-19 First Word, First Byte: On write, if
both are active, control information is completely
fetched and the first data word is not fetched. On
read if both are active, first data byte not yet trans-
mitted on interface.
Bits 20-21 Total Rec Fetch, Wr Chain PRCD: If
these bits are active, with the CDA latch; the channel
after prefetching total record and transfering control
to proper register has requested a CCWl routine and
is waiting for DTC.
Bit 22 Stop Rel: Channel has terminated an operation
on the interface. The setting of this latch normally
results in dropping sel out and either interrupting or
fetching a new CCW.
Bit 26 Stat Next: Channel has detected that the last
valid byte has been transmitted on the interface.
Bits 28-31 MP latches:
Routine MP Latch Function
Idle Cl Degates start clock signal when start,
test, or halt 1/0 instruction is detected.
C4 Unit wants service but instruction line
appears. Used for reset of channel and
handlingthe instruction.
CCWl Cl TIC
~is
detected,
CCW2 Cl CDA chaining; used in the request of unit
select.
C2 Chain check detected in CCW2; used to
end update.
C3 A channel check is _E!Csent.
C4 Starts the clock for the fourth sequence
except in Wr CDA.
Wr Fetch
Cl Data is sent from storage to B
r~ter.
C2 LlW line was sent by common channel.
Unit C2 Degates the A clock in the first sequence
Select
of two com_£lete clock
~cles.
C3
Degates the A clock in the second
sequence of two complete clock cycles.
C4 Used in the gating of the command to bus
out.
Bit 32 Sup Out: This is set:
1. If CC chaining conditions were present when
channel end status was received. Reset in next unit
selection.
2. When read CDA chaining to prevent chain
checks when starting on byte boundaries and working
with buffered units. Reset when byte counter is set
with new information.
3. For suppressing data under the following
conditions:
a. On read, if common channel allows LS
fetches with the LS buffer finish latch on;
on write, if one register is full and the
end of the record has not been reached.
b. If the multiplexor channel is in use and is
not resetting the interface and the selector
channel is transmitting data.
Bit 33 Request In: The request in line is active.
Bit 34 Svc Out Hold: This bit is set in unit selection
in response to status in (except on CU busy sequence).
Used in write operation to prevent the active state of
'svc in' until data is fetched from storage.
Bit 35 Enable Stat: This bit allows the interface
status in line to be gated to the IF controls when I/O
status may be gated to the C register.
Section H - Blank
This panel is blank on the basic system.
Section J - Local Store Chart
The printed chart on this panel shows fixed assign-
ments in the local storage area.
Appendix B--Syttem Control Panel (3/71) 149