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ROS Mode Zero/One-Cycle Tests
The zero-cycle tests are between the ROS mode
hardcore and one-cycle tests. Zero-cycle tests
insure that all triggers, for which scan-in paths
(via adder out bus or emit field) and scan-out paths
(via scan bus to SDR) are provided, can be set and
reset.
The format and mode of execution is similar for
both zero-cycle and one-cycle tests, however,
documentation for these tests is different. A diag-
nostic index, containing a suspect card list, is
provided for the zero- cycle tests. Only the index
number displayed on termination and the function
that the test was trying to perform are given.
One-cycle tests check the combinational logic
between triggers. These tests follow the zero-cycle
tests and are the last series of FLT's run. The
successful running of all previous tests (on FLT tapes
or FLT disk packs) assures that the controls and
areas needed to run the one-cycle tests are function-
ing correctly.
If
a failure which should have been
caught by hardcore or zero-cycle tests appears now,
a wrong conclusion may be reached.
Seq Ctr Mode
,----
- - - - · - - - - -
---
-
-
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A scoping index (Scopex) is provided for the one-
cycle tests. This index shows the logic that is sensi-
tive for each individual test.
The one-cycle tests are divided into a series of
segments. These segments test different areas of
logic independently. Checking for intermittent
failures is achieved by repeating each test 16 times
before reaching a conclusion as to whether the test
passed or failed.
If
the test both passes and fails,
an intermittent failure has occurred.
Figure 30 shows the method used (via FLT load)
to enter the ROS mode zero/one-cycle tests.
Zero/One-Cycle Test Methods
Each FLT cycle test uses its own individual test
program consisting of 22 consecutive test words in
storage. These cycle test programs are read into
storage (via FLT load) from the FLT ROS mode
tape or disk pack. Th.ere are approximately 181
cycle test programs on each tape record except for
the last record of each segment which is variable.
Figure 31 shows the word format of the cycle test
programs. Figure 32 is a simplified flowchart of
the FLT zero/ one-cycle tests. ROS mode zero/ one-
cycle tests are performed as follows:
Hardware
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Figures 25 and 26
FLT Load ,Then
Go to MS Mode
1-----
-K~3;-~-----:
IAR 000
L-~---~--~-----
MS Made
,----------------,
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Op 7
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(Word 2)
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Reset Bin T gr
I AR 004
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SDR to ROAR (FOB)
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Op 6
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(Word 3)
IAR 008
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Go to ROS Mode
L
____
J
QY110-FOB
(Fetch LCW)
Word 4 to SDR
QY110-F8B
(Execute LC W)
Set PSS and SS On
Set Seq Ctr to 7
SDR to ROAR (F3A)
QY150-F3A
Turn On Ignore
Lrror-1/0 Tgr
IAR OOC
FIGURE 30. FLT LOAD TO CYCLE TF.STS
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Force 2CO to ROAR
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L
_____ J
QY410-2CO
Word 5 to SDR
QYl 10..fBB
(Execute LCW)
IAR 010
SDR to ROAR (F44)
QY510..f44
Reset Pass/ Fail Tgrs
Word 6 to SDR
QY510-FBO
No Op
IAR 014
Reset Bin Tgr
and Error Reg
Branch to First Test
JAR holds address
of first word of the
desired cycle test
Start Scan - In
See Figure 32
Maintenance Features
(3/71)
51
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