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100
4MC
Osc
100
KCOOl
Latch Dela
LSAR Dela
Error Reg
50
KCOll
ROS Driver Strebe
KC011
100
100
KC021
100
100
late Reg
KC021
Nat Storage Haldoff
Nat Inhibit CPU Clack
100
Not Inhibit ROS Clack
Not Inhibit Stor
e Clack
NOTE: All timings ore oppr0>eimate. See your logic for exact timings, Page AAOOO.
FIGURE 20. CLOCK DISTRIBUTION
Latch Pulse
Set LSAR R-W
Set Error Re
ROS Sense Am
Strobe
ROS lngate Set
Sense Am Reset
Set Reg
Late Reg Set
Set Reg CPU
Free
Running
Clocks
Set Reg ROS
Non-
Set Re MS
Read Select
100
Write Selec
ROS Out ate Set
Free
Running
Clocks
Single Cycle
Storage Holdorf
Not System Reset
Set Clock
Stop Triggers
On
Gate Status
~
-t------;1
L'-----+---
- - + - - - - - ;
New CPU
Control
Status
-
--t-----t---2-7~75L__
Reset Clock
_J
y
Stop Triggers
Off
FIGURE 21. CHANGING CPU CONTROL STATUS
Maintenance Features
(3/71)
39
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